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About this book

This textbook is designed for a second course on digital systems, focused on the design of digital circuits. It was originally designed to accompany a MOOC (Massive Open Online Course) created at the Autonomous University of Barcelona (UAB), currently available on the Coursera platform. Readers will learn to develop complex digital circuits, starting from a functional specification, will know the design alternatives that a development engineer can choose to reach the specified circuit performance, and will understand which design tools are available to develop a new circuit.

Table of Contents

Frontmatter

Chapter 1. Architecture of Digital Circuits

Abstract
This chapter defines the classical partition of a digital circuit into data path and control unit. It starts with an introductory example. Then, some general considerations are presented.
Jean-Pierre Deschamps, Elena Valderrama, Lluís Terés

Chapter 2. Scheduling and Resource Assignment

Abstract
Scheduling and resource assignment are the topics of the second chapter. In particular, the concept of precedence graph is introduced, different related optimization problems are studied, and several examples are presented.
Jean-Pierre Deschamps, Elena Valderrama, Lluís Terés

Chapter 3. Pipeline

Abstract
This chapter is dedicated to pipelined circuits. The main topics are circuit segmentation, combinational circuit to pipelined circuit transformation, interconnection of pipelined circuits and self-timed circuits.
Jean-Pierre Deschamps, Elena Valderrama, Lluís Terés

Chapter 4. Loops

Abstract
The optimal implementation of loops is a basic aspect of the synthesis of digital circuits. Combinational and sequential implementations are considered. This chapter also includes the description of techniques such as loop-unrolling and digit-serial processing.
Jean-Pierre Deschamps, Elena Valderrama, Lluís Terés

Chapter 5. Other Topics of Data Path Synthesis

Abstract
Other topics of data path synthesis are treated in this chapter. For example, data path connectivity (buses), first-in first-out (FIFO) files, register files, arithmetic and logic unit (ALU), hierarchical description and sequential implementation (lower cost and longer time).
Jean-Pierre Deschamps, Elena Valderrama, Lluís Terés

Chapter 6. Control Unit Synthesis

Abstract
This chapter is dedicated to control units. Some of the studied aspects are command encoding, hierarchical control, variable-latency operations, sequencers and microprograms.
Jean-Pierre Deschamps, Elena Valderrama, Lluís Terés

Chapter 7. Input–Output Interfaces

Abstract
This chapter deals with the communication between digital circuits that are components of a complete system. A first section is dedicated to general concepts. The main section is dedicated to the definition and description of several types of buses.
Jean-Pierre Deschamps, Elena Valderrama, Lluís Terés

Chapter 8. Development Tools

Abstract
This chapter describes development tools, among others high-level synthesis (HLS), logic synthesis, functional simulation, logic simulation, timing analysis, intellectual property (IP) cores, formal verification, emulators and accelerators.
Jean-Pierre Deschamps, Elena Valderrama, Lluís Terés

Backmatter

Additional information