Computation Platforms for Multi-access Edge Computing

Table of Contents

1. Frontmatter

2. Chapter 1. Introduction

   Hideharu Amano

   Abstract

   This chapter introduces MEC (Multi-Edge access Computing) with various types of Between-Cloud-and-Edge Computing. I would like to introduce the JST Innovative Computing Technologies Supporting Society 5.0 project, which served as the impetus for writing this book.

3. Chapter 2. Multi-FPGA Platforms as a Host of MEC Architecture

   Hideharu Amano, Takuya Kojima, Mitaro Namiki

   Abstract

   This chapter introduces multi-FPGA (Field-Programmable Gate Array) systems as computing resource on MEC. First, a simple history of FPGA is presented. Then, our developed board M-KUBOS and a cluster system with the boards are introduced. Next, we present a variety of techniques, performance evaluations, and application implementation examples for efficient operation on MEC. Finally, we survey similar FPGA clusters.

4. Chapter 3. Middleware for MEC

   Midori Sugaya, Takeshi Ohkawa, Mikiko Sato, Yanzhi Li

   Abstract

   This chapter introduces MEC-RM (MEC resource manager), a middleware framework designed to facilitate the construction of edge servers equipped with a variety of hardware accelerators within multi-access edge computing (MEC)-based edge computing systems. The chapter begins by outlining the background, the challenges inherent to the deployment of heterogeneous edge infrastructures, and the objectives of our work, before proceeding to a detailed description of the proposed middleware and its application domains. MEC-RM provides a unified abstraction layer that enables seamless management of heterogeneous hardware resources, such as FPGAs and xPUs, allowing them to be treated coherently as server resources. Applications are thereby able to access and utilize these resources in a transparent and efficient manner through MEC-RM.

   In addition, the chapter presents the design of the underlying scheduler that constitutes the core of MEC-RM, as well as extensions that support the coordination of multi-FPGA environments. The effectiveness of MEC-RM was validated through empirical evaluation in a practical use case scenario, namely, AI-driven robotic services within nursing facilities. Using a fall detection application as a representative workload, we demonstrated that application control mediated by MEC-RM achieves high responsiveness and enhanced energy efficiency. Furthermore, the functionality and benefits of MEC-RM were confirmed through implementation and testing in a real-world demonstration system.

   The experimental results underscore the potential of MEC-RM as a key enabling technology for the expansion of AI-driven services across increasingly diverse and widespread edge environments. Finally, the chapter discusses future prospects for scaling edge services over broader geographic regions by leveraging the distributed control capabilities inherent in MEC-RM and concludes with a summary of key findings and avenues for future research.

5. Chapter 4. Application for a Smart City/Community

   Hiroaki Nishi, W. A. Shanaka

   Abstract

   This section presents a comprehensive exploration of smart community infrastructure, focusing on integrating multi-access edge computing (MEC) to address privacy, latency, and service scalability challenges. Through extensive use of real-world implementations and standardization efforts, we detail the conceptual evolution, structural design, and operational execution of smart communities, emphasizing their role in enhancing local quality of life (QoL) through data-driven services. The concept of a smart community evolved to encompass broader smart infrastructure, including smart transportation, agriculture, government, and healthcare. A smart community thus functions as a regionalized ecosystem where cross-domain data, from energy usage to healthcare records, is collected and analyzed to develop services that address local societal needs. To support such services, this section introduces a multilayered smart community platform. It discusses the development of common service APIs, infrastructure optimized for real-time control, and service models that are robust, interoperable, and privacy conscious. A key focus is on data granularity and latency, showing how MEC enables services with varying temporal demands—from power grid stabilization to autonomous vehicle control—by executing tasks at appropriate network layers. This section elaborates further on the implementation of open standards and the evolution of data representation protocols, including XML-based formats and IEEE standards such as 1888, 1950.X, and 1451.1.6. Our group has contributed to these standardization efforts to ensure interoperability and data utility across smart infrastructures.

   A central technical challenge discussed is anonymizing and securing personal data. The proposed architecture incorporates a hierarchical data handling mechanism where anonymization and data transformation occur as close to the data source as possible, ensuring regulatory compliance (e.g., GDPR) and minimizing risk. FPGA-based hardware accelerators and containerized applications further enhance the performance of anonymization and message processing (e.g., MQTT brokers), achieving over 100x improvements in throughput and latency under high-load conditions.

   The concept of “Transparent Add-on” is introduced to enable network-transparent edge computing, allowing for low-latency processing and secure anonymization even under encrypted communications. A method for edge decryption without modifying IoT endpoints was established, along with a revocable key system to maintain data sovereignty.

   Real-world deployments illustrate the utility of this framework. In the Urawa-Misono Smart Town project, various services were implemented using data from smart homes, commercial facilities, and public health devices. Services included thermal insulation evaluation, reinforcement learning for HVAC control, nutrition recommendation systems based on food purchases, and trajectory anonymization for location services using BLE and deep learning techniques.

   In Kurihara City, the Green Society ICT Life Infrastructure project integrated agricultural, healthcare, meteorological, and municipal data to create predictive and preventive services. Examples include heatstroke risk prediction, optimized ambulance dispatch, and personalized healthcare guidance based on ambient environmental data. A social capital index was also used to evaluate the impact of social cohesion on health outcomes.

   These services underscore the importance of dynamic data handling, secure service provisioning, and the need for modular design methodologies. A low-code development framework was proposed to support nonexpert stakeholders in service design, alongside new metrics to evaluate the trade-off between data utility and privacy. In conclusion, this section positions MEC as a pivotal enabler of smart community services by supporting flexible, low-latency, and privacy-preserving computation at the network edge. The proposed architecture balances performance, security, and usability, offering a blueprint for scalable and sustainable smart community development. This work contributes technical solutions and a comprehensive framework for designing and deploying community-centered services in an increasingly data-driven society.

6. Chapter 5. Robot Audition

   Lin Zirui, Haris Gulzar, Kazuhiro Nakadai, Hideharu Amano

   Abstract

   This chapter presents an integrated approach to accelerating robot audition technologies—Automatic Speech Recognition (ASR), Sound Source Localization (SSL), and Sound Source Separation (SSS)—on edge computing platforms using GPUs and FPGAs. For ASR, we introduce CASENet, a lightweight CNN architecture optimized for speech command classification, achieving state-of-the-art accuracy with reduced model size and computational cost. We also implement a CNN accelerator on an SoC-based edge server to further improve inference latency. For SSL and SSS, we target HARK, a widely used robot audition framework, and explore its efficient realization using parallel computing strategies on both GPU and FPGA platforms. The GPU-based implementation delivers real-time processing capability with large-scale microphone arrays, while the FPGA-based solution offers energy-efficient inference suitable for edge environments. Experimental results demonstrate significant reductions in latency and power consumption while maintaining high calculation accuracy, paving the way for robust and practical robot audition systems in diverse application scenarios.

7. Chapter 6. New Devices

   Morihiro Kuga, Masahiro Iida, Hideharu Amano

   Abstract

   This chapter introduces new devices named “SLMLET” based on a shell-rolled chip for Multi-access Edge Computing (MEC). The Shell–Role architecture has a CPU, memory, and general I/O in the Shell section, and a standard interface between the Shell section and the Role section. The Role section can accommodate a variety of applications by including user-defined purpose-specific circuits. The SLMLET has an area-efficient embedded FPGA (eFPGA) in the Role section, making it user-programmable. The eFPGA uses an original logic block architecture named Scalable Logic Cell (SLM), which can be implemented with a small number of configuration memories and a small area.

   Firstly, we introduce the concept of the SLMLET architecture and the SLM-based eFPGA-IP architecture. Then, we report on three types of prototype chips that were designed and developed in our project.

   • The first prototype was a test chip for the eFPGA-IP based on the SLM architecture, named eFPGA-IP (TEG1), explained in detail. We describe its architecture, and the issues obtained from the consideration of the evaluation results are summarized.
   • Based on the issues, eFPGA-IP (TEG2) was designed, and the second prototype was implemented as the first SLMLET-1 chip embedding eFPGA-IP (TEG2). We summarize its architecture design and discuss the issues and solutions obtained from the consideration of the evaluation results of SLMLET-1.
   • Moreover, the third prototype was implemented as the second SLMLET-2 chip embedding eFPGA-IP (TEG3). We summarize its architecture design based on the solutions from the consideration of the evaluation results of SLMLET-2.