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2015 | Book

Debug Automation from Pre-Silicon to Post-Silicon

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About this book

This book describes automated debugging approaches for the bugs and the faults which appear in different abstraction levels of a hardware system. The authors employ a transaction-based debug approach to systems at the transaction-level, asserting the correct relation of transactions. The automated debug approach for design bugs finds the potential fault candidates at RTL and gate-level of a circuit. Debug techniques for logic bugs and synchronization bugs are demonstrated, enabling readers to localize the most difficult bugs. Debug automation for electrical faults (delay faults)finds the potentially failing speedpaths in a circuit at gate-level. The various debug approaches described achieve high diagnosis accuracy and reduce the debugging time, shortening the IC development cycle and increasing the productivity of designers.

Describes a unified framework for debug automation used at both pre-silicon and post-silicon stages;Provides approaches for debug automation of a hardware system at different levels of abstraction, i.e., chip, gate-level, RTL and transaction level;Includes techniques for debug automation of design bugs and electrical faults, as well as an infrastructure to debug NoC-based multiprocessor SoCs.

Table of Contents

Chapter 1. Introduction
Abstract
The presence of Very Large Scale Integration (VLSI) circuits in our daily life increases while the size of the hardware components is shrinking. VLSI circuits are used for different applications in embedded systems such as medical electronics, automotive systems and avionics. A failure of a chip in non-critical applications may cause significant economical loss while in critical applications may also threaten the human life in the worst case. Consequently, the correct design of VLSI circuits is crucial.
Chapter 2. Preliminaries
Abstract
Each combinational circuit is represented by a directed acyclic graph C = (V, E), referred to as the circuit graph, where V is the set of circuit nodes and E ⊆ V × V, the set of edges, corresponds to the gate input-output connections in the circuit [LRS89]. For gate-level benchmarks, we consider the nodes to be gates with symmetric functions. Each node in the circuit graph is associated with a symmetric function which represents the corresponding behavior of that gate in the circuit. A symmetric function does not depend on the order of inputs but only on the sum of variables assigned to 0 or to 1, respectively.
Metadata
Title
Debug Automation from Pre-Silicon to Post-Silicon
Authors
Mehdi Dehbashi
Görschwin Fey
Copyright Year
2015
Electronic ISBN
978-3-319-09309-3
Print ISBN
978-3-319-09308-6
DOI
https://doi.org/10.1007/978-3-319-09309-3