Design and Implementation of a 16-bit Multi-mode 4-Channel Time-Interleaved Delta-Sigma Modulator with SNDR > 106 dB and DCE Compensation Based on FPGA

In this research, a second-order delta-sigma modulator (DSM) with 16-bit resolution is implemented in VHDL and based on FPGA with a time-interleaved (TI) structure. The implemented DSM operates at a frequency of 4 GHz and a bandwidth of 20 MHz. The TI architecture utilizes a single clock frequency for generating radio frequency (RF) signals. The second-order DSM has adjustable settings with three modes: low-pass (LP), band-pass (BP) at Fs/4 frequency, and high-pass (HP) for signal synthesis. To increase the sampling frequency (Fs), the TI structure is proposed with 4 channels, each of which operates at Fs/4 frequency. Since there are simple coefficients for all modes, the multiplication operation can be performed using a shifter block. To investigate the effect of duty-cycle-error (DCE) and compensate for it, different error values were applied to the modulator, and compensation was performed. In this research, a new solution is proposed to overcome the DCE effect by adjusting the filter circuit and unidirectionalizing the passband without adding extra hardware and circuit complexity. This method significantly increases the signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) values of the output of the DSM. The proposed compensation method for the BP mode is very effective and substantially improves the results. The effective number of bits (ENOBs) after compensation in the BP mode reaches 15.5 bits according to the proposed method. Simulation results in ISE show that the SNDR values for LP, BP, and HP modes are 106.10, 105.65, and 104.95 dB, respectively.