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2012 | OriginalPaper | Chapter

Design and Implementation of DVB-S2 LDPC Encoder

Authors : Ye Yuhuang, Zhou Wen, Zhuang Minmin

Published in: Recent Advances in Computer Science and Information Engineering

Publisher: Springer Berlin Heidelberg

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In this paper, a DVB-S2 LDPC encoder based on FPGA is proposed after detailed analysis of DVB-S2 LDPC code on the basis of irregular repeat accumulate (IRA) coding algorithm. This method not only uses pipeline technique combined with all parallel structures to improve the coding efficiency, but also makes use of VHDL language to achieve DVB-S2 encoder, which meets the requirements of DVB-S2 standard on the condition of low hardware resources.

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previous chapter Authentication on Presentation Layer Using Cryptographic Model for Secure Communication on FPGA Using 32-Bit Arithmetic Logic Unit and Minimized Hardware Requirement in Encryption Algorithm
next chapter Design of Data Encryption in Reconfiguration System Based on Universal HMI
Metadata
Title
Design and Implementation of DVB-S2 LDPC Encoder
Authors
Ye Yuhuang
Zhou Wen
Zhuang Minmin
Copyright Year
2012
Publisher
Springer Berlin Heidelberg
Book
Recent Advances in Computer Science and Information Engineering

Print ISBN: 978-3-642-25768-1

Electronic ISBN: 978-3-642-25769-8

Copyright Year: 2012

DOI
https://doi.org/10.1007/978-3-642-25769-8_112