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Design and Implementation on FPGA of a HW Accelerator for Post-Quantum RLWE Polynomial Operations

  • 2023
  • OriginalPaper
  • Chapter
Published in:
Authors
Stefano Di Matteo
Sergio Saponara
Riccardo Locatelli
Published in
Applications in Electronics Pervading Industry, Environment and Society
Publisher
Springer Nature Switzerland

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Abstract

The chapter delves into the design and implementation of a hardware accelerator for post-quantum RLWE polynomial operations on FPGA. It introduces the RLWE cryptosystem, highlighting its advantages over traditional schemes like RSA and ECC. The authors present the architectural design of an Arithmetic Logic Unit (ALU) for polynomial operations, utilizing the Number Theoretic Transform (NTT) to optimize polynomial multiplication. The chapter also includes a detailed implementation on Xilinx and Intel Stratix IV FPGAs, showcasing the performance of the hardware accelerator with the NewHope-1024 algorithm. Synthesis results and a comparison with state-of-the-art works are provided, demonstrating the competitive performance of the proposed design. The chapter concludes with a summary of the contributions and the potential impact on post-quantum cryptography.
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previous chapter Design and Validation of an Electronic Unit for Monitoring Water Distribution in Plastic Pipes
next chapter A Novel Front-End Circuit for the Digital Conversion of QCM-D Responses for FPGA-Based Frequency Measurements
Title
Design and Implementation on FPGA of a HW Accelerator for Post-Quantum RLWE Polynomial Operations
Authors
Stefano Di Matteo
Sergio Saponara
Riccardo Locatelli
Copyright Year
2023
Book
Applications in Electronics Pervading Industry, Environment and Society

Print ISBN: 978-3-031-30332-6

Electronic ISBN: 978-3-031-30333-3

Copyright Year: 2023

DOI
https://doi.org/10.1007/978-3-031-30333-3_8
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