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Published in:
2015 | OriginalPaper | Chapter
Design of Fully Pipelined Dual-Mode Double Precision Reduction Circuit on FPGAs
Authors : Song Guo, Yong Dou, Yuanwu Lei
Published in: Computer Engineering and Technology
Publisher: Springer Berlin Heidelberg
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This paper proposes a fully pipelined dual-mode double precision floating-point reduction circuit on the field programming gate arrays (FPGAs), which is capable of supporting one double-precision operation and two parallel single-precision operations. Through the combination of tree-traversal structure and striding mode structure, the reduction circuit can handle multiple data sets with arbitrary combination of different lengths without stall and buffer requirements, and generate in-order results. Experimental results show that the proposed reduction circuit can support the dual-mode double precision floating-point reduction at the cost of only 7% increment in the absolute latency for the double precision vector with the same length, compared with the previous single-mode double precision reduction circuits.