Design of Low Power and High-Speed CMOS Phase Frequency Detector for a PLL

High-performance phase frequency detector (PFD) is an integral part of the high-speed phase-locked loop (PLL), and their characteristics have a great impact on the performance of PLL system. The demand for the decreasing of power dissipation in CMOS design is a major challenge to optimize the circuit power consumption. In this paper, the concept of low power techniques namely, stacking and body bias have been utilized for the implementation of the proposed CMOS PFD for high-frequency applications. All the results related to the proposed designs have been obtained using TSMC 0.18 µm CMOS process. The proposed PFD design shows a remarkable reduction in power dissipation up to 172.670 pW which is significantly lower than the conventional PFD. Simulation results also show that the proposed design has wider operating frequency of 1 GHz, making it a suitable circuit for high-performance PLL systems.