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2019 | OriginalPaper | Chapter

Design Optimization of 10 nm Channel Length InGaAs Vertical Gate-All-Around Transistor (Nanowire)

Authors : Shreyas Kulkarni, Sangeeta Joshi, Dattatray Bade, Subha Subramaniam

Published in: Computing, Communication and Signal Processing

Publisher: Springer Singapore

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Abstract

This paper proposes a cylindrical vertical Gate-All-Around Transistor with nanowire of compound III-V semiconductor material In0.53Ga0.47As n-type device with channel length of 10 nm. The effect of variation of channel diameter and spacer length on the performance of the device is simulated. The device gives an acceptable Subthreshold Slope and Drain Induced Barrier Lowering along with satisfactory ION/IOFF ratio. The device is simulated in Sentaurus Synopsys using Hydrodynamic model for III-V semiconductors with Poisson equation to give the transfer characteristics.

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Metadata
Title
Design Optimization of 10 nm Channel Length InGaAs Vertical Gate-All-Around Transistor (Nanowire)
Authors
Shreyas Kulkarni
Sangeeta Joshi
Dattatray Bade
Subha Subramaniam
Copyright Year
2019
Publisher
Springer Singapore
Book
Computing, Communication and Signal Processing

Print ISBN: 978-981-13-1512-1

Electronic ISBN: 978-981-13-1513-8

Copyright Year: 2019

DOI
https://doi.org/10.1007/978-981-13-1513-8_62