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The Global Integrated Circuit Supply Chain Flow and the Hardware Trojan Attack Read chapter Read first chapter

2018 | OriginalPaper | Chapter

7. Design Techniques for Hardware Trojans Prevention and Detection at the Layout Level

Author : Hassan Salmani

Published in: Trusted Digital Circuits

Publisher: Springer International Publishing

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Abstract

Addressing hardware Trojans at the layout level has mainly focused on two sets of techniques: some techniques are to prevent hardware Trojan insertion by an untrusted manufacturer, and some other techniques are to improve hardware Trojan detection after circuit manufacturing. This chapters studies some of major work in this area and discusses their effectiveness.

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previous chapter Circuit Vulnerabilities to Hardware Trojan at the Layout Level
next chapter Trusted Testing Techniques for Hardware Trojan Detection
Literature
1.
H. Salmani, M. Tehranipoor, J. Plusquellic, A novel technique for improving hardware Trojan detection and reducing Trojan activation time. IEEE Trans. Very Large Scale Integr. Syst. 20(1), 112–125 (2012)CrossRef
2.
H. Salmani, M. Tehranipoor, Layout-aware switching activity localization to enhance hardware Trojan detection. IEEE Trans. Inf. Forensics Secur. 7(1), 76–87 (2012)CrossRef
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X. Zhang, A. Ferraiuolo, M. Tehranipoor, Detection of trojans using a combined ring oscillator network and off-chip transient power analysis. J. Emerg. Technol. Comput. Syst. 9(3), 25:1–25:20 (2013)CrossRef
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T.F. Wu, K. Ganesan, Y.A. Hu, H.S.P. Wong, S. Wong, S. Mitra, TPAD: hardware Trojan prevention and detection for trusted integrated circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(4), 521–534 (2016)CrossRef
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X. Wang, Y. Zheng, A. Basak, S. Bhunia, IIPS: infrastructure IP for secure SoC design. IEEE Trans. Comput. 64(8), 2226–2238 (2015)MathSciNetCrossRef
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K. Xiao, X. Zhang, M. Tehranipoor, A clock sweeping technique for detecting hardware Trojans impacting circuits delay. IEEE Des. Test 30(2), 26–34 (2013)CrossRef
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X. Wang, H. Salmani, M. Tehranipoor, J. Plusquellic, Hardware trojan detection and isolation using current integration and localized current analysis, in 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems (2008), pp. 87–95
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B. Cha, S.K. Gupta, Trojan detection via delay measurements: a new approach to select paths and vectors to maximize effectiveness and minimize cost, in 2013 Design, Automation Test in Europe Conference Exhibition (DATE) (2013), pp. 1265–1270
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D. Forte, C. Bao, A. Srivastava, Temperature tracking: an innovative run-time approach for hardware Trojan detection, in 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (2013), pp. 532–539
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C. Bao, D. Forte, A. Srivastava, On reverse engineering-based hardware Trojan detection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(1), 49–57 (2016)CrossRef
Metadata
Title
Design Techniques for Hardware Trojans Prevention and Detection at the Layout Level
Author
Hassan Salmani
Copyright Year
2018
Book
Trusted Digital Circuits

Print ISBN: 978-3-319-79080-0

Electronic ISBN: 978-3-319-79081-7

Copyright Year: 2018

DOI
https://doi.org/10.1007/978-3-319-79081-7_7