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2005 | OriginalPaper | Chapter

Designing On-Chip Network Based on Optimal Latency Criteria

Authors : Vu-Duc Ngo, Huy-Nam Nguyen, Hae-Wook Choi

Published in: Embedded Software and Systems

Publisher: Springer Berlin Heidelberg

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A new chip design paradigm, so called Network on Chip, has been introduced based on the demand of integration of many heterogeneous semiconductor intellectual property (IP) blocks. The Network on Chip design not only requires the good performance but also the minimization of several physical constraints such as the network latency, the used area as well as the power consumption of design. This paper analyzes the average latency of heterogeneous Network on Chip architectures in which the shortest path routing algorithm is applied. This average latency includes the queuing latency and the wire latency, and is calculated for general cases of allocating IPs onto the fixed generic switching architectures such as 2-D Mesh and Fat-Tree. With different allocation schemes of IPs, the network has different average latencies. Hence, this article presents an optimal search that adopts the Branch and Bound algorithm to find out the optimal mapping scheme to achieve the minimal network latency. This algorithm automatically map the desired IPs onto the target Network on Chip architecture with the criteria of lowest network latency. Some experiments of On Chip Multiprocessor Network application are simulated. The results show that the network latency is significantly saved with the optimized allocation scheme for the several cases of generic architectures of On Chip Multiprocessor Network application.

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Metadata
Title
Designing On-Chip Network Based on Optimal Latency Criteria
Authors
Vu-Duc Ngo
Huy-Nam Nguyen
Hae-Wook Choi
Copyright Year
2005
Publisher
Springer Berlin Heidelberg
DOI
https://doi.org/10.1007/11599555_29

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