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2024 | OriginalPaper | Chapter

5. Digital Circuits and CIM Integrated NN Processor

Author : Jinshan Yue

Published in: High Energy Efficiency Neural Network Processor with Combined Digital and Computing-in-Memory Architecture

Publisher: Springer Nature Singapore

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Abstract

This chapter first introduces the advantages of CIM in terms of energy efficiency compared to pure digital circuits based NN processors, and analyzes the deficiencies of CIM system chips, as well as the challenges of data reuse and sparsity optimization at the system level.

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previous chapter Optimized Neural Network Processor Based on Frequency-Domain Compression Algorithm

next chapter A “Digital+CIM” Processor Supporting Large-Scale NN Models

Horowitz M (2014) 1.1 computing’s energy problem (and what we can do about it). In: 2014 IEEE international solid-state circuits conference (ISSCC). IEEE, pp 10–14

Biswas A, Chandrakasan AP (2018) Conv-RAM: an energy-efficient SRAM with embedded convolution computation for low-power CNN-based machine learning applications. In: 2018 IEEE international solid-state circuits conference (ISSCC). IEEE, pp 488–490

Khwa W-S, Chen J-J, Li J-F, Si X, Yang E-Y, Sun X, Liu R, Chen P-Y, Li Q, Yu S et al (2018) A 65 nm 4 kB algorithm-dependent computing-in-memory SRAM unit-macro with 2.3 ns and 55.8 TOPS/W fully parallel product-sum operation for binary DNN edge processors. In: 2018 IEEE international solid-state circuits conference (ISSCC). IEEE, pp 496–498

Yang J, Kong Y, Wang Z, Liu Y, Wang B, Yin S, Shi L (2019) 24.4 sandwich-RAM: an energy-efficient in-memory BWN architecture with pulse-width modulation. In: 2019 IEEE international solid-state circuits conference (ISSCC). IEEE, pp 394–396

Si X, Chen J-J, Tu Y-N, Huang W-H, Wang J-H, Chiu Y-C, Wei W-C, Wu S-Y, Sun X, Liu R et al (2019) 24.5 A twin-8T SRAM computation-in-memory macro for multiple-bit CNN-based machine learning. In: 2019 IEEE international solid-state circuits conference (ISSCC). IEEE, pp 396–398

Guo R, Liu Y, Zheng S, Wu S-Y, Ouyang P, Khwa W-S, Chen X, Chen J-J, Li X, Liu L et al (2019) A 5.1 pJ/neuron 127.3 \(\upmu \)s/inference RNN-based speech recognition processor using 16 computing-in-memory SRAM macros in 65 nm CMOS. In: 2019 symposium on VLSI circuits. IEEE, pp C120–C121

Su J-W, Si X, Chou Y-C, Chang T-W, Huang W-H, Tu Y-N, Liu R, Lu P-J, Liu T-W, Wang J-H et al (2020) 15.2 A 28 nm 64 kB inference-training two-way transpose multibit 6T SRAM compute-in-memory macro for AI edge chips. In: 2020 IEEE international solid-state circuits conference (ISSCC). IEEE, pp 240–242

Si X, Tu Y-N, Huanq W-H, Su J-W, Lu P-J, Wang J-H, Liu T-W, Wu S-Y, Liu R, Chou Y-C et al (2020) 15.5 A 28 nm 64 kB 6T SRAM computing-in-memory macro with 8b MAC operation for AI edge chips. In: 2020 IEEE international solid-state circuits conference (ISSCC). IEEE, pp 246–248

Imani M, Gupta S, Rosing T (2017) Ultra-efficient processing in-memory for data intensive applications. In: 2017 54th ACM/EDAC/IEEE design automation conference (DAC). IEEE, pp 1–6

10.

Yue J, Liu Y, Yuan Z, Feng X, He Y, Sun W, Zhang Z, Si X, Liu R, Wang Z et al (2022) Sticker-IM: A 65 nm computing-in-memory NN processor using block-wise sparsity optimization and inter/intra-macro data reuse. IEEE J Sol-State Circ 57(8):2560–2573CrossRef

11.

Han S, Pool J, Tran J, Dally W (2015) Learning both weights and connections for efficient neural network. In: Advances in neural information processing systems, pp 1135–1143

12.

Wen W, Chunpeng W, Wang Y, Chen Y, Li H (2016) Learning structured sparsity in deep neural networks. Adv Neural Inf Process Syst 29:2074–2082

13.

Mao H, Han S, Pool J, Li W, Liu X, Wang Y, Dally WJ (2017) Exploring the granularity of sparsity in convolutional neural networks, pp 13–20

14.

Zhang T, Ye S, Zhang K, Tang J, Wen W, Fardad M, Wang Y (2018) A systematic DNN weight pruning framework using alternating direction method of multipliers. In: Proceedings of the European conference on computer vision (ECCV), pp 184–199

15.

Yue J, Yuan Z, Feng X, He Y, Zhang Z, Si X, Liu R, Chang M-F, Li X, Yang H et al (2020) 14.3 A 65 nm computing-in-memory-based CNN processor with 2.9-to-35.8 TOPS/W system energy efficiency using dynamic-sparsity performance-scaling architecture and energy-efficient inter/intra-macro data reuse. In: 2020 IEEE international solid-state circuits conference (ISSCC). IEEE, pp 234–236

Title: Digital Circuits and CIM Integrated NN Processor
Author: Jinshan Yue
Publisher: Springer Nature Singapore
Book: High Energy Efficiency Neural Network Processor with Combined Digital and Computing-in-Memory Architecture
Print ISBN: 978-981-9734-76-4

Electronic ISBN: 978-981-9734-77-1

Copyright Year: 2024
DOI: https://doi.org/10.1007/978-981-97-3477-1_5