Skip to main content
Top
Published in: Journal of Computational Electronics 3/2016

22-03-2016

Dual-material double-gate tunnel FET: gate threshold voltage modeling and extraction

Authors: Samantha Lubaba Noor, Samia Safa, Md. Ziaur Rahman Khan

Published in: Journal of Computational Electronics | Issue 3/2016

Log in

Activate our intelligent search to find suitable subject content or patents.

search-config
loading …

Abstract

A new analytical model for the gate threshold voltage (\(V_\mathrm{TG}\)) of a dual-material double-gate (DMDG) tunnel field-effect transistor (TFET) is reported. The model is derived by solving the quasi-two-dimensional Poisson’s equation in the lightly doped Si film and employing the physical definition of \(V_\mathrm{TG}\). A numerical simulation study of the transfer characteristics and \(V_\mathrm{TG}\) of a DMDG TFET has been carried out to verify the proposed analytical model. In the numerical calculations, extraction of \(V_\mathrm{TG}\) is performed based on the transconductance change method as already used for conventional metal–oxide–semiconductor FETs (MOSFETs). The effects of gate length scaling, Si film thickness scaling, and modification of the gate dielectric on \(V_\mathrm{TG}\) are reported. The dependence of \(V_\mathrm{TG}\) on the applied drain bias is investigated using the proposed model. The proposed model can predict the effect of variation of all these parameters with reasonable accuracy.

Dont have a licence yet? Then find out more about our products and how to get one now:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

  • über 102.000 Bücher
  • über 537 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Maschinenbau + Werkstoffe
  • Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 390 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Maschinenbau + Werkstoffe




 

Jetzt Wissensvorsprung sichern!

Springer Professional "Wirtschaft"

Online-Abonnement

Mit Springer Professional "Wirtschaft" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 340 Zeitschriften

aus folgenden Fachgebieten:

  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Versicherung + Risiko




Jetzt Wissensvorsprung sichern!

Literature
1.
go back to reference Aydin, C., Zaslavsky, A., Luryi, S., Cristoloveanu, S., Mariolle, D., Fraboulet, D., Deleonibus, S.: Lateral interband tunneling transistor in silicon-on-insulator. Appl. Phys. Lett. 84(10), 1780–1782 (2004)CrossRef Aydin, C., Zaslavsky, A., Luryi, S., Cristoloveanu, S., Mariolle, D., Fraboulet, D., Deleonibus, S.: Lateral interband tunneling transistor in silicon-on-insulator. Appl. Phys. Lett. 84(10), 1780–1782 (2004)CrossRef
2.
go back to reference Bhuwalka, K., Sedlmaier, S., Ludsteck, A., Tolksdorf, C., Schulze, J., Eisele, I.: Vertical tunnel field effect transistor. IEEE Trans. Electron Devices 51(2), 279–282 (2004)CrossRef Bhuwalka, K., Sedlmaier, S., Ludsteck, A., Tolksdorf, C., Schulze, J., Eisele, I.: Vertical tunnel field effect transistor. IEEE Trans. Electron Devices 51(2), 279–282 (2004)CrossRef
3.
go back to reference Zhang, Q., Zhao, W., Seabaugh, A.C.: Low subthreshold swing tunnel transistors. IEEE Device Lett. 27(4), 297–300 (2006)CrossRef Zhang, Q., Zhao, W., Seabaugh, A.C.: Low subthreshold swing tunnel transistors. IEEE Device Lett. 27(4), 297–300 (2006)CrossRef
4.
go back to reference Bhuwalka, K., Born, M., Schindler, M., Schmidt, M., Sulima, T., Eisele, I.: P-channel tunnel field-effect transistors down to sub-50 nm channel lengths. Jpn. J. Appl. Phys. 45(4B), 3106–3109 (2006)CrossRef Bhuwalka, K., Born, M., Schindler, M., Schmidt, M., Sulima, T., Eisele, I.: P-channel tunnel field-effect transistors down to sub-50 nm channel lengths. Jpn. J. Appl. Phys. 45(4B), 3106–3109 (2006)CrossRef
5.
go back to reference Seabaugh, A.C., Zhang, Q.: Low-voltage tunnel transistors for beyond CMOS logic. Proc. IEEE 98(12), 2095–2110 (2010)CrossRef Seabaugh, A.C., Zhang, Q.: Low-voltage tunnel transistors for beyond CMOS logic. Proc. IEEE 98(12), 2095–2110 (2010)CrossRef
6.
go back to reference Wang, P.F., Hilsenbeck, K., Nirschl, T., Oswald, M., Stepper, C., Weis, M., Schmitt Landsiedel, D., Hansch, W.: Complementary tunneling transistor for low power application. Solid State Electron. 48(12), 2281–2286 (2004)CrossRef Wang, P.F., Hilsenbeck, K., Nirschl, T., Oswald, M., Stepper, C., Weis, M., Schmitt Landsiedel, D., Hansch, W.: Complementary tunneling transistor for low power application. Solid State Electron. 48(12), 2281–2286 (2004)CrossRef
7.
go back to reference Mallik, A., Chattopadhyay, A.: Tunnel field-effect transistors for analog/mixed-signal system-on-chip applications. IEEE Trans. Electron. Devices 59(4), 888–894 (2012)CrossRef Mallik, A., Chattopadhyay, A.: Tunnel field-effect transistors for analog/mixed-signal system-on-chip applications. IEEE Trans. Electron. Devices 59(4), 888–894 (2012)CrossRef
8.
go back to reference Sedighi, B., Hu, X.S., Liu, H., Nahas, J.J., Niemier, M.: Analog circuit design using tunnel-FETs. IEEE Trans. Circuits Syst. I 62(1), 39–48 (2015)CrossRef Sedighi, B., Hu, X.S., Liu, H., Nahas, J.J., Niemier, M.: Analog circuit design using tunnel-FETs. IEEE Trans. Circuits Syst. I 62(1), 39–48 (2015)CrossRef
9.
go back to reference Shih, C.H., Chien, N.D.: Sub-10-nm tunnel field-effect transistor with graded Si/Ge heterojunction. IEEE Electron. Device Lett. 32(11), 1498–1500 (2011)CrossRef Shih, C.H., Chien, N.D.: Sub-10-nm tunnel field-effect transistor with graded Si/Ge heterojunction. IEEE Electron. Device Lett. 32(11), 1498–1500 (2011)CrossRef
10.
go back to reference Krishnamohan, T., Kim, D., Raghunathan, S., Saraswat, K.: Double gate strained-Ge hetero structure tunneling FET (TFET) with record high drive currents and \(<\)60 mV/dec subthreshold slope. In: IEDM Tech. Digest, pp. 1–3 (2008) Krishnamohan, T., Kim, D., Raghunathan, S., Saraswat, K.: Double gate strained-Ge hetero structure tunneling FET (TFET) with record high drive currents and \(<\)60 mV/dec subthreshold slope. In: IEDM Tech. Digest, pp. 1–3 (2008)
11.
go back to reference Kim, S.H., Agarwal, S., Jacobson, Z.A., Mathue, P., Hu, C., Liu, T.J.K.: Tunnel field-effect transistor with raised germanium source. IEEE Electron. Device Lett. 31(10), 1107–1109 (2010)CrossRef Kim, S.H., Agarwal, S., Jacobson, Z.A., Mathue, P., Hu, C., Liu, T.J.K.: Tunnel field-effect transistor with raised germanium source. IEEE Electron. Device Lett. 31(10), 1107–1109 (2010)CrossRef
12.
go back to reference Bhuwalka, K., Schulze, J., Eisele, I.: Scaling the vertical tunnel FET with tunnel bandgap modulation and gate workfunction engineering. IEEE Trans. Electron. Devices 52(5), 909–917 (2005)CrossRef Bhuwalka, K., Schulze, J., Eisele, I.: Scaling the vertical tunnel FET with tunnel bandgap modulation and gate workfunction engineering. IEEE Trans. Electron. Devices 52(5), 909–917 (2005)CrossRef
13.
go back to reference Boucart, K., Ionescu, A.M.: Length scaling of the double gate tunnel FET with a high-K gate dielectric. Solid State Electron. 51(11/12), 1500–1507 (2007)CrossRef Boucart, K., Ionescu, A.M.: Length scaling of the double gate tunnel FET with a high-K gate dielectric. Solid State Electron. 51(11/12), 1500–1507 (2007)CrossRef
14.
go back to reference Bhuwalka, K., Schulze, J., Eisele, I.: Performance enhancement of vertical tunnel field-effect transistor with SiGe in the delta p+ layer. Jpn. J. Appl. Phys. 43(7A), 4073–4078 (2004)CrossRef Bhuwalka, K., Schulze, J., Eisele, I.: Performance enhancement of vertical tunnel field-effect transistor with SiGe in the delta p+ layer. Jpn. J. Appl. Phys. 43(7A), 4073–4078 (2004)CrossRef
15.
go back to reference Nagavarapu, V., Jhaveri, R., Woo, J.: The tunnel source (PNPN) n-MOSFET: a novel high performance transistor. IEEE Trans. Electron. Devices 55(4), 1013–1019 (2008)CrossRef Nagavarapu, V., Jhaveri, R., Woo, J.: The tunnel source (PNPN) n-MOSFET: a novel high performance transistor. IEEE Trans. Electron. Devices 55(4), 1013–1019 (2008)CrossRef
16.
go back to reference Zhang, Q., Fang, T., Xing, H., Seabaugh, A., Jena, D.: Graphene nanoribbon tunnel transistors. IEEE Electron. Device Lett. 29(12), 1344–1346 (2008)CrossRef Zhang, Q., Fang, T., Xing, H., Seabaugh, A., Jena, D.: Graphene nanoribbon tunnel transistors. IEEE Electron. Device Lett. 29(12), 1344–1346 (2008)CrossRef
17.
go back to reference Saurabh, S., Kumar, M.J.: Novel attributes of a dual material gate nanoscale tunnel eld-effect transistor. IEEE Trans. Electron. Devices 58(2), 404–410 (2011) Saurabh, S., Kumar, M.J.: Novel attributes of a dual material gate nanoscale tunnel eld-effect transistor. IEEE Trans. Electron. Devices 58(2), 404–410 (2011)
18.
go back to reference Shen, C., Ong, S.L., Heng, C.H., Samudra, G., Yeo, Y.C.: A variational approach to the two-dimensional nonlinear Poissons equation for the modeling of tunneling transistors. IEEE Electron. Device Lett. 29(11), 1252–1255 (2008)CrossRef Shen, C., Ong, S.L., Heng, C.H., Samudra, G., Yeo, Y.C.: A variational approach to the two-dimensional nonlinear Poissons equation for the modeling of tunneling transistors. IEEE Electron. Device Lett. 29(11), 1252–1255 (2008)CrossRef
19.
go back to reference Vishnoi, R., Kumar, M.J.: A pseudo-2D analytical model of dual material gate all-around nanowire tunneling FET. IEEE Trans. Electron. Devices 61(7), 2264–2270 (2014)CrossRef Vishnoi, R., Kumar, M.J.: A pseudo-2D analytical model of dual material gate all-around nanowire tunneling FET. IEEE Trans. Electron. Devices 61(7), 2264–2270 (2014)CrossRef
20.
go back to reference Vishnoi, R., Kumar, M.J.: Compact analytical model of dual material gate tunneling eld effect transistor using interband tunneling and channel transport. IEEE Trans. Electron. Devices 61(6), 1936–1942 (2014)CrossRef Vishnoi, R., Kumar, M.J.: Compact analytical model of dual material gate tunneling eld effect transistor using interband tunneling and channel transport. IEEE Trans. Electron. Devices 61(6), 1936–1942 (2014)CrossRef
21.
go back to reference Pandey, P., Vishnoi, R., Kumar, M.J.: A full-range dual material gate tunnel field effect transistor drain current model considering both source and drain depletion region band-to-band tunneling. J. Comput. Electron. 14(1), 280–287 (2015)CrossRef Pandey, P., Vishnoi, R., Kumar, M.J.: A full-range dual material gate tunnel field effect transistor drain current model considering both source and drain depletion region band-to-band tunneling. J. Comput. Electron. 14(1), 280–287 (2015)CrossRef
22.
go back to reference Boucart, K., Ionescu, A.M.: Double-gate tunnel FET with high-k gate dielectric. IEEE Trans. Electron. Devices 54(7), 1725–1733 (2007)CrossRef Boucart, K., Ionescu, A.M.: Double-gate tunnel FET with high-k gate dielectric. IEEE Trans. Electron. Devices 54(7), 1725–1733 (2007)CrossRef
23.
go back to reference Saurabh, S., Kumar, M.J.: Impact of strain on drain current and threshold voltage of nanoscale double gate tunnel field effect transistor: theoretical investigation and analysis. Jpn. J. Appl. Phys. 48(6), 064503 (2009)CrossRef Saurabh, S., Kumar, M.J.: Impact of strain on drain current and threshold voltage of nanoscale double gate tunnel field effect transistor: theoretical investigation and analysis. Jpn. J. Appl. Phys. 48(6), 064503 (2009)CrossRef
24.
go back to reference Boucart, K., Ionescu, A.M.: A new definition of threshold voltage in tunnel FETs. Solid State Electron. 52(9), 1318–1323 (2008)CrossRef Boucart, K., Ionescu, A.M.: A new definition of threshold voltage in tunnel FETs. Solid State Electron. 52(9), 1318–1323 (2008)CrossRef
25.
go back to reference Banna, S.R., Chan, P.C.H., Ko, P.K., Nguyen, C.T., Chan, M.: Threshold voltage model for deep-submicrometer fully depleted SOI MOSFET’s. IEEE Trans. Electron. Devices 42(11), 1949–1955 (1995)CrossRef Banna, S.R., Chan, P.C.H., Ko, P.K., Nguyen, C.T., Chan, M.: Threshold voltage model for deep-submicrometer fully depleted SOI MOSFET’s. IEEE Trans. Electron. Devices 42(11), 1949–1955 (1995)CrossRef
26.
go back to reference Li, Y.-C., Zhang, H.-M., Hu, H.-Y., Zhang, Y.-M., Wang, B., Zhou, C.Y.: Double-gate tunnel field-effect transistor: gate threshold voltage modeling and extraction. J. Cent. South Univ. 21(2), 587–592 (2014)CrossRef Li, Y.-C., Zhang, H.-M., Hu, H.-Y., Zhang, Y.-M., Wang, B., Zhou, C.Y.: Double-gate tunnel field-effect transistor: gate threshold voltage modeling and extraction. J. Cent. South Univ. 21(2), 587–592 (2014)CrossRef
27.
go back to reference ATLAS Device Simulation Software: Silvaco Int. Santa Clara (2010) ATLAS Device Simulation Software: Silvaco Int. Santa Clara (2010)
28.
go back to reference Lee, W., Choi, W.Y.: Influence of inversion layer on tunneling field-effect transistors. IEEE Electron. Device Lett. 32(9), 1191–1193 (2011)MathSciNetCrossRef Lee, W., Choi, W.Y.: Influence of inversion layer on tunneling field-effect transistors. IEEE Electron. Device Lett. 32(9), 1191–1193 (2011)MathSciNetCrossRef
29.
go back to reference Knoch, J., Mantl, S., Appenzeller, J.: Impact of the dimensionality on the performance of tunneling FETs: bulk versus one-dimensional devices. Solid State Electron. 51(4), 572–578 (2007)CrossRef Knoch, J., Mantl, S., Appenzeller, J.: Impact of the dimensionality on the performance of tunneling FETs: bulk versus one-dimensional devices. Solid State Electron. 51(4), 572–578 (2007)CrossRef
30.
go back to reference Agarwal, S., Yablonovitch, E.: Fundamental tradeoff between conductance and subthreshold swing voltage for barrier thickness modulation in tunnel field effect transistors. Tech. Report (2014) Agarwal, S., Yablonovitch, E.: Fundamental tradeoff between conductance and subthreshold swing voltage for barrier thickness modulation in tunnel field effect transistors. Tech. Report (2014)
Metadata
Title
Dual-material double-gate tunnel FET: gate threshold voltage modeling and extraction
Authors
Samantha Lubaba Noor
Samia Safa
Md. Ziaur Rahman Khan
Publication date
22-03-2016
Publisher
Springer US
Published in
Journal of Computational Electronics / Issue 3/2016
Print ISSN: 1569-8025
Electronic ISSN: 1572-8137
DOI
https://doi.org/10.1007/s10825-016-0816-3

Other articles of this Issue 3/2016

Journal of Computational Electronics 3/2016 Go to the issue