4. DVFS-Oriented Scenario Applications to Processor Architectures

The objective of the present chapter is to perform synergies among system scenario methodologies and processor mapping with emphasis on DVFS. First, we exploit the system scenario methodology and combine it with a DVFS-aware scheduler to ensure timing deadlines for both hard and soft real-time processor systems. Next, we have added a novel sleep mode extension on top of the DVFS configuration to further increase our energy gains. This has been demonstrated for an SAM4L processor platform. Later, we switched to the reliability-sensitive embedded systems domain, and performed a relevant case study of a PID controller pieced together with a simple system scenario methodology to actuate DVFS and manage dependability in a successful manner. The concept of a turbo, “gas-pedal” point is also discussed. Experiments in this case were performed on pure hardware, on the NXP IMX6Q board.