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2009 | OriginalPaper | Chapter

Efficient Structures for PLL’s Loop Filter Design in FPGAs in High-Datarate Wireless Receivers – Theory and Case Study

Author : Yair Linn

Published in: Wireless Technology

Publisher: Springer US

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Abstract

In most contemporary phase lock loops (PLLs) used in high-datarate wireless receivers, some or all of the PLL’s components are implemented digitally, in particular the PLL’s loop filter. In this chapter we develop the theory behind new efficient structures for the implementation of loop filters within FPGAs (Field Programmable Gate Arrays) using fixed-point arithmetic. The theory is then investigated via a case study, in which we present FPGA hardware mapping results that show that employing the proposed method results in a decrease of more than 70% in the logic gate count needed as compared to the conventional implementation.

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Footnotes
1
As for symbol timing clocks, these are usually derived from crystal oscillators, which also usually have negligible phase noise at a frequency offset of several kHz.
 
2
Here for simplicity we are multiplying two positive numbers. When one or more of the numbers is negative then tricky sign and sign-extension issues are present. These issues are quite easy and straightforward to resolve, and this subject is treated in Section 8.2.1.
 
3
The fact that we have over-engineered the filter by adding eight more LSB bits to the datapath to represent the fractional part of the results of operations (see Fig. 9, Section 7.4) also helps since this reduces the error magnitude of an LSB error by 256, i.e., more than 2 orders of magnitude.
 
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Metadata
Title
Efficient Structures for PLL’s Loop Filter Design in FPGAs in High-Datarate Wireless Receivers – Theory and Case Study
Author
Yair Linn
Copyright Year
2009
Publisher
Springer US
Book
Wireless Technology

Print ISBN: 978-0-387-71786-9

Electronic ISBN: 978-0-387-71787-6

Copyright Year: 2009

DOI
https://doi.org/10.1007/978-0-387-71787-6_8