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About this book

This book provides an overview of emerging topics in the field of hardware security, such as artificial intelligence and quantum computing, and highlights how these technologies can be leveraged to secure hardware and assure electronics supply chains. The authors are experts in emerging technologies, traditional hardware design, and hardware security and trust. Readers will gain a comprehensive understanding of hardware security problems and how to overcome them through an efficient combination of conventional approaches and emerging technologies, enabling them to design secure, reliable, and trustworthy hardware.

Table of Contents

Frontmatter

Chapter 1. Blockchain-Enabled Electronics Supply Chain Assurance

Abstract
Electronic systems are ubiquitous today, playing an irreplaceable role in our personal lives as well as in critical infrastructures such as power grid, satellite communication, and public transportation. In the past few decades, the software running on these systems has received quite a bit of attention regarding security. Hardware has been assumed to be trustworthy and reliable “by default” without really analyzing the vulnerabilities in the electronics supply chain. With the rapid globalization of the semiconductor industry, it has become challenging to ensure the integrity and security of hardware. In this chapter, we discuss the integrity concerns associated with a globalized electronics supply chain. We divide the supply chain into distinct participants and entities and analyze the vulnerabilities and threats associated with each stage. To address the concerns of the supply chain integrity, we analyze the prospect of a blockchain-based certificate authority framework that can be used to manage critical chip information such as electronic chip identification (ECID), chip grade, transaction time, etc. The decentralized nature of the data-centric verification framework can mitigate most threats of electronics supply chain, such as recycling, remarking, cloning, and overproduction.
Fahim Rahman, Mark Tehranipoor

Chapter 2. Digital Twin with a Perspective from Manufacturing Industry

Abstract
In the era of intelligent manufacturing, Digital Twin is an emerging technology that has attracted a huge attention in industry. Digital Twin has been discussed extensively, but they are separated in different research areas. This paper reviews the existing literature and classifies them in the context of evolution, application, definition, framework, and design process of DT. We also discuss some security issues in DT. A specific view from semiconductor manufacturing is provided to see why DT is necessary, and several research opportunities are presented as inspirations for future work.
Haibo Wang, Shigang Chen, Md Sami Ul Islam Sami, Fahim Rahman, Mark Tehranipoor

Chapter 3. Trillion Sensors Security

Abstract
The advancement of ubiquitous computing in the Internet of Things (IoT) and Cyber-Physical Systems (CPS) applications boosted the number of connected devices increased in the last decade. The prevalence use of IoT applications with pervasive sensing enables billions of devices connected to the internet, and each device may have multiple sensors attached, which lead us to the age of trillion sensors. However, the widespread use of sensors in critical infrastructures and applications, such as smart grid, smart city, industry 4.0 (smart manufacture), and healthcare, also raises additional security concerns. It is necessary to understand the infrastructure consisting of trillions of sensors to identify and thwart the potential threats before they occur. In this chapter, we aim to provide a detailed survey of the applicability and capabilities of the trillion sensors in diversified application domains. We present a comprehensive taxonomy of sensors introduced in [3] that have been widely adopted in IoT/CPS applications. We illustrate the IoT/CPS architecture and the underlying vulnerabilities in the trillion sensors era. We analyze and discuss future directions and solutions for solving security issues.
Pinchen Cui, Ujjwal Guin, Mark Tehranipoor

Chapter 4. Security of AI Hardware Systems

Abstract
Artificial intelligence (AI) systems are changing our lives. Coming with the benefits, challenges on AI security raise concerns as AI systems are not only accessing personal and sensitive data, they are also to be deployed on systems related to life safety (e.g., autonomous vehicles and medical systems) and critical infrastructures. In this chapter, we will start from a brief introduction to modern AI systems, review reported AI security issues, and discuss possible countermeasures.
Haoting Shen

Chapter 5. Machine Learning in Hardware Security

Abstract
The ever-increasing demand for higher computing capabilities constantly pushes the development of the semiconductor industry and is making modern hardware an extremely complicated artifact. However, with the increased complexity of today’s hardware systems, their security is also challenged by various vulnerabilities coming from different perspectives. Hardware-related security, as an emerging research area, has been gaining more attention during the past decades. As a result, more novel attacks and corresponding countermeasures are being proposed almost every day. The complexity of modern hardware systems makes many conventional methodologies reaching the limit of their analytical capabilities, and new powerful methods and tools are in urgent need to study hardware security problems. Thanks to the significant development of machine learning, numerous advanced analytical methodologies and tools become directly available and applicable to hardware security research, which greatly enhances the ability of both hardware designers and attackers. To present readers the important role played by machine learning in today’s hardware security, this chapter presents the application of machine learning in different hardware security areas, such as IP protection, Trojan detection, side-channel analysis/attacks, hardware security primitives, and architectural vulnerabilities, and highlights future research directions.
Shijin Duan, Zhengang Li, Yukui Luo, Mengshu Sun, Wenhao Wang, Xue (Shelley) Lin, Xiaolin Xu

Chapter 6. Security Assessment of High-Level Synthesis

Abstract
Securing intellectual property (IP) blocks have become a huge concern for the designers due to increasing attacks at different stages of the design. This wide array of attacks from IP piracy, counterfeiting, reverse engineering to overproduction has prompted designers to look into protection mechanisms to limit unauthorized access to the actual design. Logic locking/obfuscation is such a technique that protects designs from unauthorized usages by embedding locking keys into the design that are unknown to adversaries. However, the majority of the proposed locking techniques work at the gate-level of the design, and it has been shown that the correct keys can be successfully retrieved through various adversarial attacks such as SAT attacks, removal attacks, and reverse engineering. In this chapter, we propose a locking technique at a higher level of abstraction and show that using high-level synthesis, this technique is far more resilient towards different attacks and provides better control in terms of performance parameters to the designer compared to other techniques. The key element of this technique is locking the design at higher levels of abstractions (i.e., C/C++) when the designers have a better understanding of the design’s critical functions/information. In the next step, a high-level synthesis (HLS) tool is used to automatically generate locked RTL modules from an untimed C/C++ description. The proposed framework is dependent on HLS. As a result, design security also depends on a secure HLS process. For this purpose, we also provide a detailed security assessment on the HLS process and show potential vulnerabilities during its translation. We also present some verification approaches to address these vulnerabilities to secure the design and provide a robust framework for IP protection.
M. Rafid Muttaki, Nitin Pundir, Mark Tehranipoor, Farimah Farahmandi

Chapter 7. CAD for Side-Channel Leakage Assessment

Abstract
Power side-channel attacks (SCAs) have been proven to be effective at extracting secret keys from hardware implementations of cryptographic algorithms. Therefore, it is imperative to evaluate if the hardware is vulnerable to SCAs during its design and validation stages. Ideally, this validation should be performed as early as the pre-silicon stage. In this chapter, we present some existing techniques for PSCL assessment and discuss in depth on two CAD frameworks called SCRIPT and RTL-PSC which evaluates information leakage through side-channel analysis at pre-silicon stage.
Adib Nahiyan, Miao (Tony) He, Jungmin Park, Mark Tehranipoor

Chapter 8. Post-Quantum Hardware Security

Physical Security in Classic vs. Quantum Worlds
Abstract
This chapter concerns how the evolution of quantum technology could influence the field of hardware security. Besides this question, the impact of hardware security on the quantum systems, and in particular, quantum cryptosystems, is discussed in detail. This impact goes beyond the direct effect of quantum computers on the security of cryptosystems since it also encompasses the risk imposed by physical attacks known in the classic world. In this respect, the main message conveyed by this chapter is that post-quantum cryptosystems can suffer from not only quantum-enhanced attacks, but also classic physical attacks; hence, in their design, it is crucial to revisit the adversary models and design flows.
Ana Covic, Sreeja Chowdhury, Rabin Yu Acharya, Fatemeh Ganji, Domenic Forte

Chapter 9. Post-Quantum Cryptographic Hardware and Embedded Systems

Abstract
When evaluating different cryptosystems, one primary metric is the cost to deploy the scheme in today’s software or hardware platforms. Given the option, hardware acceleration is typically preferred as optimizing a cryptosystem’s computations in logical gates leads to improvements in performance, power, and energy. Here, we survey the progress on acceleration of post-quantum key establishment cryptosystems in hardware. We examine the critical computations in the third round of NIST’s PQC standardization competition, how to efficiently speed these up in hardware, and the state-of-the-art results of these schemes.
Brian Koziel, Mehran Mozaffari Kermani, Reza Azarderakhsh

Chapter 10. Neuromorphic Security

Abstract
Heretofore, CMOS devices, circuits and architectures, experienced an accelerated technological evolution, with hardware security policies struggling to catch up to these advances. Hence, time and again, traditional computing platforms have fallen prey to security threats. With neuromorphic computing, the amalgamation of novel non-Von Neumann architectures, new post-CMOS nano-ionic devices, and an innovative software stack truly marks the beginning of a new era in computing system design. On the flip side, the simultaneous introduction of (1) unorthodox architectures, (2) circuits designed using novel devices, and (3) devices fabricated from unfamiliar materials, into a potentially flawed and untrustworthy system-on-chip (SoC) design space, can stir up a hornet’s nest of security threats.
With neuromorphic hardware expected to form the backbone of life-critical systems in healthcare, military and automotive industries, the potential ramifications of security vulnerabilities arising from following the same precedent of evolution as CMOS based architectures can prove catastrophic. Uncovering security vulnerabilities in the emerging neuromorphic computing paradigm, and understanding the impact of security on system characteristics will be instrumental in shaping our design practices. In this chapter, we examine security concerns in emerging neuromorphic systems with emphasis on vulnerabilities arising from devices, circuits, architectures and supporting sub-systems.
Rajesh J. S., Koushik Chakraborty, Sanghamitra Roy

Chapter 11. Homomorphic Encryption

Abstract
Out of all the encryption techniques available, homomorphic encryption is distinctive, and often called the Holy Grail of encryption, as it allows the manipulation of encrypted data without the need to decrypt it first. Homomorphic encryption has tremendous potential in cloud-based services such as storage, computation, artificial intelligence, location-based recommendations, etc. as it enables any entity to perform diverse operations (e.g., do search, query or sort, run mathematical functions, etc.) on the data without revealing its original content. Because of the security and privacy concerns, the full potential of cloud computing and cloud-based services is yet to be fully utilized. As full homomorphic encryption enables execution of arbitrary functions on the encrypted data while ensuring robust privacy, it can truly realize the concept of a connected world and internet-of-everything by assuring the corporate as well as the general users that their data will always remain secure and private. Although the idea of full homomorphic encryption was there since 1978, the theoretical demonstration of its practical implementation occurred relatively recently in 2009. The widespread enthusiasm in the research community that has ensued in full homomorphic encryption since then, need to be sustained to make it faster and, therefore, transparent to the regular user. In this chapter, a short review of homomorphic encryption is presented.
Mehdi Sadi

Chapter 12. Software Security with Hardware in Mind

Abstract
Software is ubiquitous, spanning from our everyday life to space station. With a significant increase in the processing power of modern computing devices, the number of software that deals with sensitive data rises exponentially, providing incentives for performing attacks against these systems. The devices may face various adversarial attacks based on cache side channel, Spectre, Meltdown, Ransomware, buffer and integer overflow, etc. The primary objective of software security is to enhance security in such a way so that software becomes resilient against various malicious attacks during run-time. However, many software-based approaches have been implemented to protect the software from the adversarial attacks. Unfortunately, these techniques cannot provide comprehensive protection as most software vulnerabilities arise not only for the development faults but also for weak hardware architecture. Additionally, software-based approaches may create backdoors for future attacks. Therefore, it is not practical to enhance security only from a software or hardware point of view in a mutually exclusive fashion. This chapter explores various software and hardware vulnerabilities to understand the potential exploitable scenarios better and protect the software from hardware and software perspectives.
Muhammad Monir Hossain, Fahim Rahman, Farimah Farahmandi, Mark Tehranipoor

Chapter 13. Firmware Protection

Abstract
Assurance of an embedded system’s security depends mainly on the protection scheme of the firmware. Enhancing the security of the hardware alone cannot protect the systems from various adversarial attacks, while keeping the firmware undefensive against tampering, cloning, or reverse engineering. For developing a counterfeit embedded application, the principal target is to retrieve the original firmware from the authentic hardware platform so that the adversary can maximize the profits while investing significantly less. However, remarkable researches have been done to protect the firmware. There are both software- and hardware-assisted approaches for firmware protection. The traditional software-based approaches cannot protect the control flow and sensitive information entirely from being leaked out. Furthermore, software-based approaches incur significant memory and performance overhead. This chapter focuses on some robust approaches for firmware protection that leverage the intrinsic hardware signatures to bind the firmware with the trusted hardware platform. In these schemes, the firmware does not run on counterfeit hardware systems or vice versa.
Muhammad Monir Hossain, Fahim Rahman, Farimah Farahmandi, Mark Tehranipoor

Chapter 14. Security of Emerging Memory Chips

Abstract
Memory chips play a critical role in performance and energy because they are the fundamental bottlenecks in computing systems. Several emerging memory chips such as Magneto-resistive Random-Access Memory (MRAM), Resistive RAM (ReRAM), Phase-Change Memory (PCM), and Ferroelectric RAM (FRAM) have been proposed to replace mainstream memory chips to overcome the limitations of the existing memory chips such as high leakage current, a large amount of energy consumption, lack of scalability, etc. These emerging memory chips possess several advantageous features such as non-volatility, high density, scalability, long endurance, ultralow-power operation, read/write current asymmetry, high write current, etc. However, some of these new exclusive features in the emerging memory device and architecture may introduce new vulnerabilities that can be detrimental for security and safety. This chapter will focus on the security vulnerabilities of emerging non-volatile memory chips and discuss the existing countermeasures to make the computing systems robust against various attacks.
Farah Ferdaus, Md Tauhidur Rahman

Chapter 15. Security of Analog, Mixed-Signal, and RF Devices

Abstract
This chapter provides a comprehensive overview to the field of hardware security, specifically focusing on the side-channel analysis (SCA) and physically unclonable functions (PUFs). We investigate the different mechanisms of analog phenomena causing vulnerabilities like side-channels, counterfeit ICs, denial-of-service (DoS) attacks. Parallelly, this chapter also dives into the security features that analog circuits can provide, which can be utilized to protect against power and electromagnetic (EM) SCA attacks, or realizing physically unclonable functions (PUFs) for device authentication.
Debayan Das, Baibhab Chatterjee, Shreyas Sen

Chapter 16. Analog IP Protection and Evaluation

Abstract
The increasing cost of manufacturing integrated circuits (IC) has forced many companies to go fabless. With the outsourcing of IC fabrication in a globalized/distributed design flow, including multiple (potentially untrusted) entities, the semiconductor industry faces several challenging security threats. This fragility in the face of weak state-of-the-art intellectual property (IP) protection has resulted in hardware security vulnerabilities, such as IP piracy, overbuilding, reverse engineering, and hardware Trojans. To address these issues at the hardware level, different design-for-trust (DfTr) techniques, such as IC metering, watermarking, IC camouflaging, split manufacturing, and logic locking have been proposed to secure digital circuits. Though there are many DfTr techniques to secure digital circuits, there is a great dearth of techniques for analog and mixed-signal (AMS) IP protection. However, analog ICs are more prone to supply-chain attacks than digital ICs as they are easier to reverse engineer. This high vulnerability is due to their low transistor count compared to their digital counterparts. To address the impact of process variations, they also have predefined layout patterns, e.g., common-centroid. Analog ICs are not simple, although they have less number of transistors. Even with only hundreds of transistors, analog IC design requires highly experienced designers and a long time, as analog behaviors are quite complicated.
N. G. Jayasankaran, A. Sanabria-Borbón, E. Sánchez-Sinencio, J. Hu, J. Rajendran

Chapter 17. Application of Optical Techniques to Hardware Assurance

Abstract
The backside of modern Integrated Circuits (ICs) is becoming an open backdoor for malicious hardware attackers to take advantage of. Aided by new Failure Analysis (FA) optical techniques, e.g., Photon Emission Analysis (PEA), optical probing, and Laser Fault Injection (LFI), hackers pose a serious threat to the confidentiality, integrity, and availability of sensitive information on a chip. In addition, optical backside attacks can risk semiconductor intellectual property (IP) protection mechanisms, such as logic locking. In this chapter, we start by reviewing some of the FA techniques through the perspective of optical attack. We then outline an attack model, discuss combinational and sequential logic locking, and focus on the corresponding state space obfuscation methodology. Attack procedures are described on how to break into the obfuscation systems, and the existing countermeasures and their limitations are discussed. Finally, the hardware assurance view point is discussed, in which a new approach for hardware Trojan detection is covered.
Leonidas Lavdas, M. Tanjidur Rahman, Navid Asadizanjani

Chapter 18. Computer Vision for Hardware Security

Abstract
The application of computer vision to hardware security has the potential to address the limitations of both electrical testing and traditional physical inspection approaches to hardware security. This chapter begins by providing an overview of basic computer vision concepts as well as a description of pipeline tasks. Examples of three hardware security applications where the application of computer vision has been explored, namely integrated circuit counterfeit detection, hardware Trojan detection, and printed circuit board assurance, are discussed in detail. Lastly, the chapter concludes with a discussion of the challenges of applying computer vision to hardware security and provides suggestions for future research directions.
Hangwei Lu, Daniel E. Capecci, Pallabi Ghosh, Domenic Forte, Damon L. Woodard

Chapter 19. Asynchronous Circuits and Their Applications in Hardware Security

Abstract
Asynchronous circuits are increasingly used as an efficient countermeasure for a wide range of threats in the microelectronics industry. This chapter provides a tutorial on the basic concepts of asynchronous design, with an elaboration on their potential benefits and drawbacks. The chapter also provides a literature survey on applying asynchronous circuits to hardware security, potential security flaws in asynchronous design, and a discussion on proposed mitigation techniques.
Eslam Yahya Tawfik, Waleed Khalil

Chapter 20. Microfluidic Device Security

Abstract
Functional diversification is expected to drive the growth of hardware computing beyond the end of Moore’s law. Medical application is expected to be a system driver of such diversification. Microfluidic technologies enable miniaturization of laboratory-based biochemical protocols. A microfluidic biochip or lab-on-a-chip (LoC) performs biochemical reactions by consuming nano-/pico-liter volume of reagents. These platforms use less volume of samples and reagents and provide quicker results than the traditional lab. Also, these platforms enable automation that reduces the reliance on high-skilled personnel. Digital microfluidic biochip (DMFB) and continuous flow-based microfluidic biochip (CFMB) are examples of such biochip platforms. CFMBs manipulate fluid flow through a network of micro-channel by actuating pressure-driven micro-valves. DMFB offers a programmable fluidic platform in which discrete fluid droplets can be manipulated through electrical actuations.
Mohammed Shayan, Tung-Che Liang, Ramesh Karri, Krishnendu Chakrabarty

Backmatter

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