Enabling Trust for Advanced Semiconductor Solutions Based on Physical Layout Verification

With growing connectivity in consumer and industrial applications, the need for security rises proportionally. Compromises in security design of e.g. autonomous driving systems endanger not only material goods but may threaten personal life of humans. Besides the demand for functional safety of complex, connected systems, cyber security is paramount. As the traditional verification flow is only dealing with functionality, reliability and safety aspects, a trusted design flow extends this by adding aspects of hardware vulnerabilities in verification and certification. Consequently, without full trust in the globally distributed development and production process, semiconductor manufacturers need to check that no malicious modifications are inserted. Physical layout verification is achieved via a comparison of the recovered chip layout extracted from an application against the design data. To enable trust, a comprehensive figure of merit has been defined to evaluate the correlation of the layout extraction to design data. Using this figure of merit (FoM), it is shown on a 40 nm sample that ultra-high scanning speeds still deliver adequate image quality.