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2024 | OriginalPaper | Chapter

3. Energy-Efficient NN Processor by Optimizing Data Reuse for Specific Convolutional Kernels

Author : Jinshan Yue

Published in: High Energy Efficiency Neural Network Processor with Combined Digital and Computing-in-Memory Architecture

Publisher: Springer Nature Singapore

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Abstract

This chapter studies the data reuse characteristics of digital ASIC NN processors, and proposes a CNN processor, named KOP3, that is optimized for specific convolutional kernel sizes. Compared to previous NN processors that achieve higher flexibility but sacrifice a certain energy efficiency, the proposed KOP3 architecture trade-offs the flexibility for different convolutional kernel sizes with energy efficiency.

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Literature
1.
go back to reference Chen Y-H, Krishna T, Emer J, Sze V (2016) 14.5 Eyeriss: an energy-efficient reconfigurable accelerator for deep convolutional neural networks. In: 2016 IEEE international solid-state circuits conference (ISSCC). IEEE, pp 262–264 Chen Y-H, Krishna T, Emer J, Sze V (2016) 14.5 Eyeriss: an energy-efficient reconfigurable accelerator for deep convolutional neural networks. In: 2016 IEEE international solid-state circuits conference (ISSCC). IEEE, pp 262–264
2.
go back to reference Moons B, Uytterhoeven R, Dehaene W, Verhelst M (2017). 14.5 ENVISION: a 0.26-to-10 TOPS/W subword-parallel dynamic-voltage-accuracy-frequency-scalable convolutional neural network processor in 28 nm FDSOI. In: 2017 IEEE international solid-state circuits conference (ISSCC). IEEE, pp 246, 247 Moons B, Uytterhoeven R, Dehaene W, Verhelst M (2017). 14.5 ENVISION: a 0.26-to-10 TOPS/W subword-parallel dynamic-voltage-accuracy-frequency-scalable convolutional neural network processor in 28 nm FDSOI. In: 2017 IEEE international solid-state circuits conference (ISSCC). IEEE, pp 246, 247
3.
go back to reference Yuan Z, Yue J, Yang H, Wang Z, Li J, Yang Y, Guo Q, Li X, Chang M-F, Yang H et al (2018) STICKER: a 0.41–62.1 TOPS/W 8 bit neural network processor with multi-sparsity compatible convolution arrays and online tuning acceleration for fully connected layers. In: 2018 IEEE symposium on VLSI circuits. IEEE, pp 33–34 Yuan Z, Yue J, Yang H, Wang Z, Li J, Yang Y, Guo Q, Li X, Chang M-F, Yang H et al (2018) STICKER: a 0.41–62.1 TOPS/W 8 bit neural network processor with multi-sparsity compatible convolution arrays and online tuning acceleration for fully connected layers. In: 2018 IEEE symposium on VLSI circuits. IEEE, pp 33–34
4.
go back to reference Chen T, Du Z, Sun N, Wang J, Wu C, Chen Y, Temam O (2014) Diannao: a small-footprint high-throughput accelerator for ubiquitous machine-learning. In: Proceedings of the 19th international conference on architectural support for programming languages and operating systems, pp 269–284 Chen T, Du Z, Sun N, Wang J, Wu C, Chen Y, Temam O (2014) Diannao: a small-footprint high-throughput accelerator for ubiquitous machine-learning. In: Proceedings of the 19th international conference on architectural support for programming languages and operating systems, pp 269–284
6.
go back to reference Yue J, Liu Y, Yuan Z, Wang Z, Guo Q, Li J, Yang C, Yang H (2018) A 3.77 tops/w convolutional neural network processor with priority-driven kernel optimization. IEEE Trans Circ Syst II Express Briefs 66(2):277–281 Yue J, Liu Y, Yuan Z, Wang Z, Guo Q, Li J, Yang C, Yang H (2018) A 3.77 tops/w convolutional neural network processor with priority-driven kernel optimization. IEEE Trans Circ Syst II Express Briefs 66(2):277–281
7.
go back to reference Pullini A, Conti F, Rossi D, Loi I, Gautschi M, Benini L (2017) A heterogeneous multicore system on chip for energy efficient brain inspired computing. IEEE Trans Circ Syst II Express Briefs 65(8):1094–1098 Pullini A, Conti F, Rossi D, Loi I, Gautschi M, Benini L (2017) A heterogeneous multicore system on chip for energy efficient brain inspired computing. IEEE Trans Circ Syst II Express Briefs 65(8):1094–1098
8.
go back to reference Du Z, Fasthuber R, Chen T, Ienne P, Li L, Luo T, Feng X, Chen Y, Temam O (2015) Shidiannao: shifting vision processing closer to the sensor. In: Proceedings of the 42nd annual international symposium on computer architecture, pp 92–104 Du Z, Fasthuber R, Chen T, Ienne P, Li L, Luo T, Feng X, Chen Y, Temam O (2015) Shidiannao: shifting vision processing closer to the sensor. In: Proceedings of the 42nd annual international symposium on computer architecture, pp 92–104
9.
go back to reference Krizhevsky A, Sutskever I, Hinton GE (2012) ImageNet classification with deep convolutional neural networks. In: Advances in neural information processing systems, pp 1097–1105 Krizhevsky A, Sutskever I, Hinton GE (2012) ImageNet classification with deep convolutional neural networks. In: Advances in neural information processing systems, pp 1097–1105
10.
go back to reference He K, Zhang X, Ren S, Sun J (2016) Deep residual learning for image recognition. In: Proceedings of the IEEE conference on computer vision and pattern recognition, pp 770–778 He K, Zhang X, Ren S, Sun J (2016) Deep residual learning for image recognition. In: Proceedings of the IEEE conference on computer vision and pattern recognition, pp 770–778
11.
go back to reference Yuan Z, Liu Y, Yue J, Li J, Yang H (2017) Coral: coarse-grained reconfigurable architecture for convolutional neural networks. In: 2017 IEEE/ACM international symposium on low power electronics and design (ISLPED). IEEE, pp 1–6 Yuan Z, Liu Y, Yue J, Li J, Yang H (2017) Coral: coarse-grained reconfigurable architecture for convolutional neural networks. In: 2017 IEEE/ACM international symposium on low power electronics and design (ISLPED). IEEE, pp 1–6
Metadata
Title
Energy-Efficient NN Processor by Optimizing Data Reuse for Specific Convolutional Kernels
Author
Jinshan Yue
Copyright Year
2024
Publisher
Springer Nature Singapore
DOI
https://doi.org/10.1007/978-981-97-3477-1_3