Skip to main content
Disciplines
Automotive Business IT + Informatics Construction + Real Estate Electrical Engineering + Electronics Energy + Sustainability Insurance + Risk Finance + Banking Management + Leadership Marketing + Sales Mechanical Engineering + Materials
Events
DE
EN
Books
Journals
Topic Page
Marketing
Start single access now
Access for companies
EXTENDED SEARCH
Log in
Top
Computing
Published in: Computing 6/2015

01-06-2015

Energy reduction in 3D NoCs through communication optimization

Authors: Ozcan Ozturk, Ismail Akturk, Ismail Kadayif, Suleyman Tosun

Published in: Computing | Issue 6/2015

Log in

Activate our intelligent search to find suitable subject content or patents.

search-config
loading …

Abstract

Network-on-Chip (NoC) architectures and three-dimensional (3D) integrated circuits have been introduced as attractive options for overcoming the barriers in interconnect scaling while increasing the number of cores. Combining these two approaches is expected to yield better performance and higher scalability. This paper explores the possibility of combining these two techniques in a heterogeneity aware fashion. Specifically, on a heterogeneous 3D NoC architecture, we explore how different types of processors can be optimally placed to minimize data access costs. Moreover, we select the optimal set of links with optimal voltage levels. The experimental results indicate significant savings in energy consumption across a wide range of values of our major simulation parameters.
previous article Using constraint programming for the design of network-on-chip architectures
next article System on chip failure rate assessment using the executable model of a system

Dont have a licence yet? Then find out more about our products and how to get one now:

Springer Professional "Wirtschaft"

Online-Abonnement

Mit Springer Professional "Wirtschaft" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 340 Zeitschriften

aus folgenden Fachgebieten:

  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Versicherung + Risiko




Jetzt Wissensvorsprung sichern!

inform now

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 390 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Maschinenbau + Werkstoffe




 

Jetzt Wissensvorsprung sichern!

inform now

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

  • über 102.000 Bücher
  • über 537 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Maschinenbau + Werkstoffe
  • Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

inform now
Literature
1.
ITRS (2013) International technology roadmap for semiconductors
2.
Pavlidis V, Friedman E (2007) 3-d Topologies for networks-on-chip. Very large scale integration (VLSI) systems. IEEE Trans On 15(10):1081–1090
3.
Davis W, Wilson J, Mick S, Xu J, Hua H, Mineo C, Sule A, Steer M, Franzon P (2005) Demystifying 3d ics: the pros and cons of going vertical. Design Test Comput IEEE 22(6):498–510CrossRef
4.
Li F, Nicopoulos C, Richardson T, Xie Y, Narayanan V, Kandemir M (2006) Design and management of 3d chip multiprocessors using network-in-memory. In: Computer architecture, 2006. ISCA ’06. 33rd international symposium on, pp 130–141
5.
Murali S, Benini L, De Micheli G (2010) Design of networks on chips for 3d ics. In: Proceedings of the 2010 Asia and South Pacific design automation conference, pp 167–168
6.
Park D, Eachempati S, Das R, Mishra AK, Xie Y, Vijaykrishnan N, Das CR (2008) Mira: a multi-layered on-chip interconnect router architecture. SIGARCH Comput Archit News 36:251–261CrossRef
7.
Loi I, Angiolini F, Benini L (2008) Developing mesochronous synchronizers to enable 3d nocs. In: Design, automation and test in Europe, 2008. DATE ’08, pp 1414–1419
8.
Borkar S (2011) 3d integration for energy efficient system design. In: design automation conference (DAC), 2011 48th ACM/EDAC/IEEE, pp 214–219
9.
Vivet P, Dutoit D, Thonnart Y, Clermidy F (2011) 3d NoC using through silicon via: an asynchronous implementation. In: VLSI and system-on-chip (VLSI-SoC), 2011 IEEE/IFIP 19th international conference on, pp 232–237
10.
Ebrahimi M, Daneshtalab M, Liljeberg P, Plosila J, Tenhunen H (2013) Cluster-based topologies for 3d networks-on-chip using advanced inter-layer bus architecture. J Comput Syst Sci 79(4):475–491CrossRefMATHMathSciNet
11.
Daneshtalab M, Ebrahimi M, Plosila J (2012) Hibs: novel inter-layer bus structure for stacked architectures. In: 3D systems integration conference (3DIC), 2011 IEEE, international, pp 1–7
12.
Coskun AK, Ayala JL, Atienza D, Rosing TS, Leblebici Y (2009) Dynamic thermal management in 3d multicore architectures. DATE 1410–1415
13.
Akbari S, Shafiee A, Fathy M, Berangi R (2012) Afra: a low cost high performance reliable routing for 3d mesh nocs. DATE 332–337
14.
Wu TH, Davoodi A, Linderoth JT (2009) Grip: scalable 3d global routing using integer programming. DAC 320–325
15.
Ozturk O, Wang F, Kandemir M, Xie Y (2006) Optimal topology exploration for application-specific 3d architectures. In: Design automation, 2006. Asia and South Pacific conference on (2006)
16.
Akturk I, Ozturk O (2013) Ilp-based communication reduction for heterogeneous 3d network-on-chips. PDP 514–518
17.
Soteriou V, Peh LS (2004) Design-space exploration of power-aware on/off interconnection networks. In: Computer design: VLSI in computers and processors, 2004. ICCD 2004. Proceedings. IEEE international conference on, pp 510–517
18.
19.
Hu J, Shin Y, Dhanwada N, Marculescu R (2004) Architecting voltage islands in core-based system-on-a-chip designs. In: Low power electronics and design, 2004. ISLPED ’04. Proceedings of the 2004 international symposium on, pp 180–185
20.
Amarasinghe SP, Anderson JM, Lam MS, wen Tseng C (1993) An overview of the suif compiler for scalable parallel machines. In: Proceedings of the seventh SIAM conference on parallel processing for scientific computing, pp 662–667
21.
Wang HS, Zhu X, Peh LS, Malik S (2002) Orion: a power-performance simulator for interconnection networks. In: Microarchitecture, 2002. (MICRO-35). Proceedings 35th annual IEEE/ACM international symposium on, pp 294–305. doi:10.​1109/​MICRO.​2002.​1176258
22.
23.
Metadata
Title
Energy reduction in 3D NoCs through communication optimization
Authors
Ozcan Ozturk
Ismail Akturk
Ismail Kadayif
Suleyman Tosun
Publication date
01-06-2015
Publisher
Springer Vienna
Published in
Computing / Issue 6/2015
Print ISSN: 0010-485X
Electronic ISSN: 1436-5057
DOI
https://doi.org/10.1007/s00607-013-0378-1

Other articles of this Issue 6/2015

Computing 6/2015 Go to the issue

OriginalPaper

TurboLock: increasing associativity of lock table in transactional memory

OriginalPaper

Using constraint programming for the design of network-on-chip architectures

Editorial

Special issue on on-chip parallel and network-based systems

OriginalPaper

A Light-weight fault-tolerant routing algorithm tolerating faulty links and routers

OriginalPaper

Decentralized task scheduling for a fixed priority multicore embedded RTOS

OriginalPaper

Design and implementation of counting networks

Premium Partner

    Image Credits