Equivalent circuit modeling and relaxation dynamics of Au/Ti/AlN/n-Si MOS structures

The impedance behavior of the Au/Ti/AlN/n-Si MOS structure was modeled using a canonical \(R_{s} - (R_{p} ||C_{p}\)) equivalent circuit, as shown in Fig. 1. Here\(R_{s}\) represents the contact resistance,\(R_{p}\) denotes the space-charge region resistance, and\(C_{p}\) reflects the dielectric response of the AlN interlayer. This configuration is widely adopted in dielectric and semiconductor impedance studies due to its ability to capture both resistive and capacitive dynamics across frequency and bias domains [38, 39].

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The complex impedance \(\left( {Z^{*} = Z^{\prime} + iZ^{\prime\prime}} \right)\) of the equivalent circuit shown in Fig. 1 can be expressed analytically as Eqs. 1–3 [16, 17]:where \({R}_{s}\) is the series resistance,\(R_{p}\) is the parallel resistance associated with the space-charge region,\(C_{p}\) is the parallel capacitance of the dielectric layer, and\(\omega = 2\pi f\) is the angular frequency. Separating the real and imaginary components yields

These expressions capture the frequency-dependent relaxation dynamics of the system. At low frequencies, the denominator in both expressions is small, leading to high impedance values dominated by interfacial polarization. As frequency increases, the capacitive reactance diminishes, and the impedance approaches the resistive limit defined by\(R_{s}\) [29]. Series resistance \(\left( {R_{s} } \right)\) arises from the resistance of the ohmic and the rectifier metal contacts, the bulk resistance of the semiconductor and the contact resistance between the metal contact and the semiconductor.

The capacitance–voltage (C–V) behavior of the Au/Ti/AlN/n‑Si MOS structure was systematically examined under a range of bias voltages (–2 V to + 4 V) and modulation frequencies spanning 10 kHz to 1 MHz. The resulting profiles, shown in Fig. 2, reveal a clear dependence on both applied voltage and signal frequency, reflecting the interplay between depletion dynamics, interfacial trap states, and dielectric polarization mechanisms [40, 41]. At low frequencies (10–70 kHz), the capacitance values are notably higher, particularly in the depletion and accumulation regions. This enhancement is attributed to the ability of interface states—located at the AlN/Si boundary—to follow the slow AC signal and contribute to charge modulation. These states act as auxiliary polarization centers, effectively increasing the measured capacitance beyond its geometric value. Such behavior is well documented in wide-bandgap MIS systems, where trap-assisted polarization dominates the low-frequency response [42].

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As the frequency increases beyond 300 kHz, a systematic suppression of capacitance is observed. This trend arises from the inability of slower traps to respond within the shortened signal period, thereby reducing their contribution to the overall dielectric response. In this regime, the measured capacitance reflects primarily the intrinsic properties of the AlN interlayer and the depletion capacitance of the n‑Si substrate. The transition from trap-dominated to bulk-controlled behavior is a hallmark of frequency-resolved dielectric analysis and has been previously reported in AlN-based capacitive stacks and Schottky interfaces [24, 27]. The inversion region, corresponding to negative bias values, exhibits a nearly flat capacitance profile across all frequencies. This plateau behavior indicates that minority carrier generation is insufficient to modulate the capacitance dynamically, and the response is governed by deep-level traps and fixed charges. The lack of frequency dependence in this region further confirms the limited mobility and slow reconfiguration of trapped carriers under reverse bias conditions. It is also noteworthy that the accumulation region, observed at higher-positive biases, shows a frequency-dependent roll-off in capacitance. In order to discern whether the measured capacitance originates purely from the geometrical attributes of the device or is significantly influenced by interfacial contributions, the geometric capacitance \(\left( {C_{geo} } \right)\) may also be evaluated. This quantity is governed by the dielectric constant, the active device area, and the thickness of the dielectric layer and is expressed as in Eq. 4 [43, 44]:where\(\in_{0} = 8.854 \times 10\,^{ - 12}\) F/m is the permittivity of free space,\(\in_{r}\) denotes the relative dielectric constant of AlN (typically reported in the range of 8–9), “A” is the active device area, and “d” is the thickness of the AlN layer. The resulting geometric capacitance is approximately 2.8 pF. In contrast, the experimentally extracted capacitance values obtained from equivalent circuit fitting remain nearly constant at ~ 2.2 nF across all bias conditions. This discrepancy of nearly three orders of magnitude unequivocally demonstrates that the measured capacitance cannot be explained by geometry alone. Such divergence highlights the dominant role of trap-assisted polarization and dipolar reorientation processes at the AlN/Si interface [45]. The apparent constancy of\(C_{p}\) with bias, despite its large deviation from the geometric value, indicates that interfacial states contribute substantially to the dielectric response, particularly at low frequencies where their dynamics can follow the applied AC signal. This observation is consistent with prior reports onAl₂O₃- and HfO₂ -based MOS structures, where interfacial polarization mechanisms similarly elevate the effective capacitance beyond its geometric baseline [46, 47]. Overall, the systematic comparison between calculated and measured values provides compelling evidence that the AlN dielectric behaves not as a simple geometric capacitor, but as a complex system in which interfacial dynamics are integral to the overall response. The elevated capacitance at low frequencies and its suppression at high frequencies confirm the critical role of interfacial states in shaping the dielectric behavior. These findings validate the presence of active trap ensembles at the AlN/Si interface and show the importance of frequency-resolved analysis in assessing the true dielectric performance of wide-bandgap MOS systems.

The bias-dependent impedance behavior of the Au/Ti/AlN/n-Si MOS structure was systematically evaluated across a broad frequency spectrum ranging from 10 kHz to 1 MHz. As shown in Fig. 3, the impedance magnitude \(|Z|\) exhibits a pronounced dependence on both the applied DC bias and the excitation frequency. At lower frequencies (10–100 kHz), the impedance values are significantly elevated in the depletion and inversion regions, indicating limited carrier mobility and enhanced interfacial polarization. As the frequency increases, |Z| decreases sharply, particularly near 0 V, suggesting a transition from capacitive-to-resistive transport mechanisms [48].

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The observed impedance drops near “0 V” across all frequencies (Fig. 4) reflects the onset of accumulation, where majority carriers dominate transport and the dielectric response becomes less frequency sensitive. This crossover is consistent with the corner frequency, \(f_{c}\) defined as Eq. 5 [49, 50]:

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As observed in Fig. 4, the impedance magnitude \(|Z|\) and phase angle \(\theta\) exhibit a clear frequency-dependent transition, with a distinct corner frequency identified near 7.24 kHz. This threshold marks the shift from capacitive-to-resistive behavior, where the dielectric response begins to stabilize. For the AlN-based MOS structure, the estimated corner frequency lies within the range of 7–8 kHz, coinciding with the peak positions observed in the imaginary impedance spectra (\(Z^{\prime\prime}\) vs. log f). This value is significantly higher than those reported for\(Cd_{x} Zn_{1 - x} O\)/p-Si andCrO₃/p-Si systems, where corner frequencies typically remain below 5 kHz due to higher trap densities and slower relaxation kinetics [51, 52]. The monotonic decrease in\(\left| Z \right|\) with increasing frequency further substantiates the capacitive character of the AlN dielectric layer.

At high bias and high frequency, the impedance reaches a saturation regime, indicating that the AlN layer sustains a stable dielectric response with minimal trap-induced dispersion. Such behavior is characteristic of a well-passivated interface and confirms the suitability of AlN as a high-performance gate dielectric material. As frequency increases, the impedance magnitude decreases systematically, particularly in the depletion and inversion regions. This reduction is directly linked to the capacitive nature of the structure, where the reactance is given by \(X_{c} = 1/wC\), \(\omega = 2\pi f\) and diminishes with increasing angular frequency [27, 53]. In the accumulation region (positive bias), the impedance becomes relatively flat and frequency-independent, suggesting that the device response is governed by bulk conduction pathways dominated by series resistance and geometric capacitance. The convergence of impedance values at high bias and high frequency reflects enhanced carrier injection and narrowing of the depletion width, which together facilitate low-resistance conduction channels.

The phase angle θ, defined as the angular displacement between the applied voltage and resulting current in an AC-driven system, serves as a sensitive indicator of the dominant transport mechanism—capacitive or resistive—within the MOS structure. Mathematically, it is expressed as Eq. 6 [54]:

At low frequencies and reverse bias, the imaginary component\(Z^{\prime\prime}\) dominates due to slow trap dynamics and interfacial polarization, resulting in\(\theta \to - 90^\circ\), characteristic of ideal capacitive behavior. This is clearly observed in Fig. 5, where the phase angle curves at 10–100 kHz exhibit deep negative values in the depletion and inversion regions. As the bias increases toward accumulation, and the frequency rises beyond 300 kHz, the real component\(Z^{\prime}\) becomes dominant, driving\(\theta \to 0^\circ\). This transition reflects the suppression of capacitive reactance and the emergence of resistive conduction pathways, primarily governed by series resistance \({R}_{s}\) and bulk carrier injection. The frequency-dependent evolution of θ across bias confirms the capacitive-to-resistive crossover predicted by the model. The steepest transitions occur near 0 V, where the depletion region collapses and the dielectric response shifts from trap limited to bulk controlled. Similar phase angle behavior has been reported in oxide-based MOS structures, includingAl₂O₃/p-Si and HfO₂ /n-Si systems, where bias-induced modulation of interfacial states and carrier injection leads to comparable angular transitions. The sharpness and monotonicity of the phase shift in the AlN-based structure further suggest a well-passivated interface with minimal distributed relaxation [47, 55].

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To further elucidate the underlying transport mechanisms and validate the single relaxation time assumption, the real and imaginary components of the impedance were analyzed as a function of frequency under varying bias conditions. These results are presented in Fig. 6a and Fig. 6b, respectively. The frequency dependence of the real and imaginary components of impedance provides a direct probe into the relaxation dynamics and conduction pathways within the MOS structure.

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Figure 6a illustrates the behavior of\(Z^{\prime}\) across a logarithmic frequency range (log f = 2 to 6) for bias voltages between 1 and 4 V. At low frequencies (log f < 3),\(Z^{\prime}\) remains high and nearly constant, consistent with the low-frequency limit of Eq. (2), where the denominator is small and the resistive contribution from \(R_{p}\) dominates. This regime reflects trap-limited conduction and space-charge polarization, where carriers are unable to respond dynamically to the AC field. As frequency increases,\(Z^{\prime}\) decreases sharply, particularly between log f ≈ 3.0 and 4.5. This decline corresponds to the onset of AC conductivity, where the capacitive reactance diminishes and the resistive component transitions toward the series resistance\(R_{s}\). Beyond log\(f \approx 4.5\),\(Z^{\prime}\) stabilizes, approaching the high-frequency limit, \(Z^{\prime} \approx R_{s}\) indicating that the impedance is governed primarily by intrinsic conduction pathways. The bias dependence is evident: higher voltages yield lower\(Z^{\prime}\) plateaus and earlier onset of decline, consistent with reduced\(R_{p}\) due to enhanced carrier injection [56].

Figure 6b presents the imaginary component\(Z^{\prime\prime}\) under the same bias conditions. Each curve exhibits a distinct peak centered around log f ≈ 3.5, corresponding to the relaxation frequency\(f_{\max }\) of the system. This peak arises from the dynamic reorientation of dipolar entities and trapped charges, which respond to the AC field within a specific time window. The peak condition is defined by Eq. 7 [16, 17]:

The position of the peak shifts toward lower frequencies with increasing bias, indicating that the relaxation process slows under forward bias. This shift is attributed to the reduction in bulk resistance and saturation of trap states, which alter the time constants of the system. The relaxation time \(\tau\) is extracted using Eq. 8 [16, 17]:

The sharpness and uniqueness of the\(Z^{\prime\prime}\) peak across all bias levels confirm the presence of a single dominant relaxation mechanism, consistent with Debye-type behavior. Similar peak dynamics have been reported in ZnS nanoparticles and magnetic ceramics, where bias-induced modulation of trap ensembles leads to comparable shifts in relaxation frequency [57, 58]. Together, Fig. 6a and b validates the analytical predictions of Eq. 5 and confirm that the AlN-based MOS structure exhibits a coherent, bias-tunable relaxation response. The agreement between experimental data and model behavior supports the use of a single-time constant equivalent circuit and reinforces the physical interpretation of trap-limited conduction transitioning to bulk-controlled transport under increasing frequency and bias [59].

The relaxation times (τ) extracted from the imaginary impedance peaks in Fig. 6-b are consolidated in Table 1, offering a quantitative perspective on the bias-dependent dynamics of the AlN-based MOS structure. These values were calculated using the standard Debye relation in Eq-7, where\(f_{\max }\) is the frequency at which the imaginary part of the impedance reaches its maximum. The corresponding relaxation time τ thus reflects the characteristic time scale of charge redistribution and dipolar reorientation within the dielectric stack.

As shown in Table 1, the extracted\(f_{\max }\) values range from approximately 8200 Hz at 2.0 V to 6000 Hz at 4.0 V, yielding relaxation times between 19.41 μs and 26.54 μs. The trend is non-monotonic:\(\tau\) initially decreases with increasing bias, reaching a minimum near 2.0 V, and then increases again at higher voltages. This behavior is physically consistent with a two-regime response: In the low-to-moderate bias range (1.0–2.0 V), the narrowing of the depletion region and enhanced carrier injection reduce the effective resistance R_p, accelerating the relaxation process. This leads to shorter \(\tau\) values, as observed in Cd-doped ZnO and Al₂O₃systems where similar bias-induced acceleration has been reported [51, 55]. In the high bias regime (≥ 3.5 V), trap saturation and field-induced dipolar reconfiguration begin to dominate. These effects introduce additional time constants or slow down the reorientation kinetics, resulting in longer relaxation times. Comparable behavior has been observed in magnetic ceramics and complex oxide interfaces, where high-field conditions activate deeper trap states or induce structural rearrangements.

Importantly, the smooth evolution of \(\tau\) across bias, without abrupt discontinuities or multi-peak behavior, confirms the presence of a single dominant relaxation mechanism. This is a hallmark of Debye-type systems, where the dielectric response is governed by a unique time constant rather than a distribution. The consistency between the \(\tau\) values derived from f_max and those obtained independently from the fitted circuit parameters (R_p C_p) further validates the single-time constant equivalent circuit model. From a device engineering perspective, the relatively narrow range of \(\tau\) values (19–27 μs) across the entire bias window indicates that the AlN dielectric maintains a stable and predictable response under varying operating conditions. This is particularly advantageous for high-frequency applications, where relaxation time uniformity ensures minimal phase distortion and energy loss.

Cole–Cole model is one of the analysis methods widely used in electrical impedance applications. This approach is also used to evaluate the parameters of the equivalent electrical circuit. The drawing of the\(Z^{\prime\prime}\) value against the\(Z^{\prime\prime}\) value for dielectric systems in the complex plane is called the Cole–Cole plot. The semicircle of the Cole–Cole graph can be defined as follows Eq. 9 [16, 17]:

This equation represents a circle with center at (R_s+R_p/2) and a radius of R_p/2 and is used to extract the parameters of the equivalent circuit given in Eq. 9. The R_p and C_p can be determined from the diameter of the semicircle and the frequency value corresponding to the maximum value of the semicircle, respectively. Figure 7 illustrates the Cole–Cole representations (\(Z^{\prime\prime}\)versus\(Z^{\prime}\)) of the MOS capacitor measured under various DC bias conditions. In each case, the plots consistently display a single, well-defined semicircular arc. Such behavior is characteristic of systems governed by a unique relaxation pathway, confirming that the dielectric response of the structure is dominated by a single relaxation process across the applied bias range [60, 61]. The radius of semicircle increases with increasing applied positive voltage. Cole–Cole plots can be well fitted by the proposed equivalent circuit.

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In addition, the circuit parameters including R_p, C_p, and R_s obtained from the fit of Equations with experimental results at different DC bias voltages are given in Table 2. As demonstrated in Table 2,\(C_{p}\) values remain almost the same for all bias voltages, while R_p and R_s values vary depending on the bias voltage. The R_s value is quite small compared to the\(R_{p}\) value. At the same time, τ represents the relaxation time constant and its values calculated from the equation:\(R_{p} \cdot C_{p}\) are given in Table 2. The obtained τ values are quite consistent with the τ values determined from the equation:\(\omega \tau = 2\pi f_{\max } \cdot \tau = 1\) using the maximum frequency given in Fig. 6b.

To complement the impedance-based relaxation study, the bias dependence of interface trap density (\(D_{it}\)) was evaluated using the normalized D_it–V profile as shown in Fig. 8. This plot provides a direct measure of trap activity at the AlN/Si interface under varying electric fields. The normalized D_it values were extracted using the analytical relation in Eq. 10 [14, 20]:

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As illustrated in Fig. 7, the normalized \({D}_{it}\) exhibits a monotonic decrease with increasing bias voltage, ranging from 1.0 V to 4.0 V. This trend reflects the progressive passivation or deactivation of interface states under forward bias. At low bias (1.0–2.0 V), the trap density remains relatively high, consistent with the elevated capacitance and relaxation activity observed in Figs. 2 and 6. These traps are energetically aligned with the mid-gap region of the n-Si substrate and can dynamically exchange charge with the conduction band under weak electric fields. As the bias increases beyond 2.5 V, the D_it values decline sharply, indicating that the interface states either become filled or energetically inaccessible. This behavior is consistent with the narrowing of the depletion region and the shift of the quasi-Fermi level toward the conduction band, which suppresses trap-mediated transitions. The reduction in D_it correlates strongly with the increase in R_p and τ observed in Table 2, suggesting that trap deactivation leads to a more resistive and slower dielectric response. Such bias-dependent D_it suppression has been reported in high-k dielectrics including Al₂O₃, HfO₂, and La₂O₃, where field-induced dipole alignment and charge redistribution reduce the effective trap cross-section [23, 53]. In the case of AlN, the wide bandgap and low native defect density further enhance this effect, yielding a stable interface with minimal trap reactivation under high bias.

From a device engineering perspective, the decreasing D_it profile confirms the suitability of AlN as a gate dielectric for high-frequency and low-leakage applications. The ability to suppress interface trap activity under operating bias conditions ensures minimal energy loss, reduced hysteresis, and improved signal fidelity [7, 53]. This behavior is particularly advantageous in RF and power electronics, where dielectric stability under dynamic bias is critical to maintaining phase coherence and minimizing parasitic losses. The observed relaxation times, which remain within a narrow and predictable range across the entire bias spectrum, further reinforce the reliability of AlN-based MOS structures under varying electrical stress. Moreover, the consistency between relaxation times extracted from both impedance peak positions and equivalent circuit fitting underscores the robustness of the single-time constant model. The absence of multi-peak behavior or abrupt transitions in the impedance spectra suggests that AlN interfaces are not only structurally uniform but also electronically well passivated. This uniformity translates into reproducible device performance, reduced process variability, and enhanced scalability for integrated circuit applications.