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Altered PPI Due to Mutations in hPER2 and CKI Delta Locus, Causing ASPS Read chapter Read first chapter

2017 | OriginalPaper | Chapter

Estimation of MOS Capacitance Across Different Technology Nodes

Authors : Sarita Kumari, Rishab Mehra, Amit Krishna Dwivedi, Aminul Islam

Published in: Proceedings of the First International Conference on Intelligent Computing and Communication

Publisher: Springer Singapore

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Abstract

This paper presents an in-depth analysis of NMOS capacitances across various technology nodes and device parameters which are extracted for different operating regions namely accumulation, cutoff, saturation and triode, while keeping the aspect ratio same for each transistor. Since MOS capacitances are the key parameters for estimating process development, material selection and device modeling, this paper enlists their variation with gate-to-source voltage (VGS) while keeping drain-to-source voltage (VDS) constant. This paper also aims to present the impact of capacitance variation on device performance that includes operating speed, power consumption, delay product and so on. The simulations results have been extensively verified using HSPICE simulator @ various technology nodes.

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previous chapter Implication of Performance Appraisal Process on Employee Engagement Mediated Through the Development and Innovation Oriented Culture: A Study on the Software Professionals of IT Companies in West Bengal
next chapter Cross-Coupled Dynamic CMOS Latches: Scalability Analysis
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Metadata
Title
Estimation of MOS Capacitance Across Different Technology Nodes
Authors
Sarita Kumari
Rishab Mehra
Amit Krishna Dwivedi
Aminul Islam
Copyright Year
2017
Publisher
Springer Singapore
Book
Proceedings of the First International Conference on Intelligent Computing and Communication

Print ISBN: 978-981-10-2034-6

Electronic ISBN: 978-981-10-2035-3

Copyright Year: 2017

DOI
https://doi.org/10.1007/978-981-10-2035-3_30

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