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2014 | OriginalPaper | Chapter

6. Event-Driven Successive Charge Redistribution Schemes for Clockless Analog-to-Digital Conversion

Authors : Dariusz Kościelnik, Marek Miśkowicz

Published in: Design, Modeling and Testing of Data Converters

Publisher: Springer Berlin Heidelberg

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Abstract

The analog-to-digital conversion methods based on event-driven successive charge redistribution schemes are presented in the study. In the proposed schemes, the charge redistribution is forced by a self-timed mechanism that substitutes a clock in driving a converter operation. One of important implications is that the converter almost does not consume energy in breaks between conversion cycles that can be triggered irregularly in time.

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Literature
1.
go back to reference Matsuzawa, A.A.: Design challenges of analog-to-digital converters in nanoscale CMOS. IEICE Trans. Electron. E90-C, 779–785 (2007) Matsuzawa, A.A.: Design challenges of analog-to-digital converters in nanoscale CMOS. IEICE Trans. Electron. E90-C, 779–785 (2007)
2.
go back to reference Yang, H.Y., Sarpeshkar, R.: A time-based energy-efficient analog-to-digital converter. IEEE J. Solid-State Circ. 40(8), 1590–1601 (2005)CrossRef Yang, H.Y., Sarpeshkar, R.: A time-based energy-efficient analog-to-digital converter. IEEE J. Solid-State Circ. 40(8), 1590–1601 (2005)CrossRef
3.
go back to reference Lazar, A.A., Tóth, L.T.: Perfect recovery and sensitivity analysis of time encoded bandlimited signals. IEEE Trans. Circ. Syst. -I: Regul. Pap. 52, 2060–2073 (2005) Lazar, A.A., Tóth, L.T.: Perfect recovery and sensitivity analysis of time encoded bandlimited signals. IEEE Trans. Circ. Syst. -I: Regul. Pap. 52, 2060–2073 (2005)
4.
go back to reference Lazar, A.A., Simonyi, E.K., Toth, L.T.: Time encoding of bandlimited signals, an overview. In: Proceedings of the Conference on Telecom. Systems, Modeling and Analysis (2005) Lazar, A.A., Simonyi, E.K., Toth, L.T.: Time encoding of bandlimited signals, an overview. In: Proceedings of the Conference on Telecom. Systems, Modeling and Analysis (2005)
5.
go back to reference Lazar, A.A., Pnevmatikakis, E.A.: Video time encoding machines. IEEE Trans. Neural Networks 22, 461–473 (2011)CrossRef Lazar, A.A., Pnevmatikakis, E.A.: Video time encoding machines. IEEE Trans. Neural Networks 22, 461–473 (2011)CrossRef
6.
go back to reference Taillefer, C.S., Roberts, G.W.: Delta–Sigma A/D conversion via time-mode signal processing. IEEE Trans. Circ. Syst.-I: Regul. Pap. 56(9), 1908–1920 (2009) Taillefer, C.S., Roberts, G.W.: Delta–Sigma A/D conversion via time-mode signal processing. IEEE Trans. Circ. Syst.-I: Regul. Pap. 56(9), 1908–1920 (2009)
7.
go back to reference Kościelnik, D., Miśkowicz, M.: Asynchronous sigma-delta analog-to-digital converter based on the charge pump integrator. Analog Integr. Circ. Sig. Process 55, 223–238 (2008)CrossRef Kościelnik, D., Miśkowicz, M.: Asynchronous sigma-delta analog-to-digital converter based on the charge pump integrator. Analog Integr. Circ. Sig. Process 55, 223–238 (2008)CrossRef
8.
go back to reference Daniels, J., Dehaene, W., Steyaert, M.S.J., Wiesbauer, A.: A/D conversion using asynchronous delta-sigma modulation and time-to-digital conversion. IEEE Trans. Circ. Syst.-II: Exp Briefs 57(9), 2404–2412 (2010)MathSciNetCrossRef Daniels, J., Dehaene, W., Steyaert, M.S.J., Wiesbauer, A.: A/D conversion using asynchronous delta-sigma modulation and time-to-digital conversion. IEEE Trans. Circ. Syst.-II: Exp Briefs 57(9), 2404–2412 (2010)MathSciNetCrossRef
9.
go back to reference Hernandez, L., Prefasi, E.: Analog-to-digital conversion using noise shaping and time encoding. IEEE Trans. Circ. Syst.-I: Regul. Pap. 55(7), 2026–2037 (2008) Hernandez, L., Prefasi, E.: Analog-to-digital conversion using noise shaping and time encoding. IEEE Trans. Circ. Syst.-I: Regul. Pap. 55(7), 2026–2037 (2008)
10.
go back to reference Pekau, H., Yousif, A., Haslett, J.W.: A CMOS integrated linear voltage-to-pulse-delay-time converter for time based analog-to-digital converters. Proc. IEEE Int Symp. Circ. Syst. 2006, 2373–2376 (2006) Pekau, H., Yousif, A., Haslett, J.W.: A CMOS integrated linear voltage-to-pulse-delay-time converter for time based analog-to-digital converters. Proc. IEEE Int Symp. Circ. Syst. 2006, 2373–2376 (2006)
11.
go back to reference Ravinuthula, V., Harris, J.G.: Time-based arithmetic using step functions. Proc. IEEE Int. Symp. Circ. Syst. ISCAS 2004, 305–308 (2004) Ravinuthula, V., Harris, J.G.: Time-based arithmetic using step functions. Proc. IEEE Int. Symp. Circ. Syst. ISCAS 2004, 305–308 (2004)
12.
go back to reference Allier, E., Sicard, G., Fesquet, L., Renaudin, M.: A new class of asynchronous A/D converters based on time quantization. Proc. IEEE Int. Symp. Asynchronous Circ. Syst. ASYNC 2003, 196–205 (2003) Allier, E., Sicard, G., Fesquet, L., Renaudin, M.: A new class of asynchronous A/D converters based on time quantization. Proc. IEEE Int. Symp. Asynchronous Circ. Syst. ASYNC 2003, 196–205 (2003)
13.
go back to reference Kozmin, K., Johansson, J., Delsing, J.: Level-crossing ADC performance evaluation toward ultrasound application. IEEE Trans. Circ. Syst. Part I: Regul. Pap. 56, 1708–1719 (2009) Kozmin, K., Johansson, J., Delsing, J.: Level-crossing ADC performance evaluation toward ultrasound application. IEEE Trans. Circ. Syst. Part I: Regul. Pap. 56, 1708–1719 (2009)
14.
go back to reference Guan, K.M., Kozat, S.S., Singer, A.C.: Adaptive reference levels in a level-crossing analog-to-digital converter, EURASIP J. Adv. Sig. Processing 2008, 11 (Article ID 513706) (2008) Guan, K.M., Kozat, S.S., Singer, A.C.: Adaptive reference levels in a level-crossing analog-to-digital converter, EURASIP J. Adv. Sig. Processing 2008, 11 (Article ID 513706) (2008)
15.
go back to reference Kurchuk, M., Tsividis, Y.: Signal-dependent variable-resolution clockless A/D conversion with application to continuous-time digital signal processing. IEEE Trans. Circ. Syst. Part I: Regul. Pap. 57, 982–991 (2010) Kurchuk, M., Tsividis, Y.: Signal-dependent variable-resolution clockless A/D conversion with application to continuous-time digital signal processing. IEEE Trans. Circ. Syst. Part I: Regul. Pap. 57, 982–991 (2010)
16.
go back to reference Trakimas, M., Sonkusale, S.R.: An adaptive resolution asynchronous ADC architecture for data compression in energy constrained sensing applications. IEEE Trans. Circ. Syst. Part I: Regul. Pap. 58, 921–934 (2011) Trakimas, M., Sonkusale, S.R.: An adaptive resolution asynchronous ADC architecture for data compression in energy constrained sensing applications. IEEE Trans. Circ. Syst. Part I: Regul. Pap. 58, 921–934 (2011)
17.
go back to reference Senay, S., Chaparro, L.F., Sun, M., Sclabassi, R.J.: Adaptive level-crossing sampling and reconstruction. Proc. of European Signal Processing Conf. EUSIPCO 1296–1300 (2010) Senay, S., Chaparro, L.F., Sun, M., Sclabassi, R.J.: Adaptive level-crossing sampling and reconstruction. Proc. of European Signal Processing Conf. EUSIPCO 1296–1300 (2010)
18.
go back to reference Tsividis, Y.: Event-driven data acquisition and digital signal processing: a tutorial. IEEE Trans. Circ. Syst II: Exp Briefs 57, 577–582 (2010)MathSciNetCrossRef Tsividis, Y.: Event-driven data acquisition and digital signal processing: a tutorial. IEEE Trans. Circ. Syst II: Exp Briefs 57, 577–582 (2010)MathSciNetCrossRef
19.
go back to reference Miśkowicz, M.: Send-on-delta concept: an event-based data reporting strategy. Sensors 6, 49–63 (2006)CrossRef Miśkowicz, M.: Send-on-delta concept: an event-based data reporting strategy. Sensors 6, 49–63 (2006)CrossRef
20.
go back to reference Kościelnik, D., Miśkowicz, M.: Method and apparatus for conversion of portion of electric charge to digital word. PCT Patent Application WO 2011/152743, 2011 Kościelnik, D., Miśkowicz, M.: Method and apparatus for conversion of portion of electric charge to digital word. PCT Patent Application WO 2011/152743, 2011
21.
go back to reference Kościelnik, D., Miśkowicz, M.: Method and apparatus for conversion of time interval to digital word. PCT Patent Application WO 2011/152744, 2011 Kościelnik, D., Miśkowicz, M.: Method and apparatus for conversion of time interval to digital word. PCT Patent Application WO 2011/152744, 2011
22.
go back to reference Kościelnik, D., Miśkowicz, M.: Method and apparatus for conversion of voltage value to digital word. PCT Patent Application WO 2011/152745, 2011 Kościelnik, D., Miśkowicz, M.: Method and apparatus for conversion of voltage value to digital word. PCT Patent Application WO 2011/152745, 2011
23.
go back to reference Kościelnik, D., Miśkowicz, M.: A new method of charge-to-digital conversion. Proc. IEEE Int. Mixed-Signals, Sens. Syst. Test Workshop IMS3TW (2010) Kościelnik, D., Miśkowicz, M.: A new method of charge-to-digital conversion. Proc. IEEE Int. Mixed-Signals, Sens. Syst. Test Workshop IMS3TW (2010)
24.
go back to reference Kościelnik, D., Miśkowicz, M.: A clockless time-to-digital converter. Proc. IEEE Convention Elect. Electron. Eng. Israel IEEEI 2010, 516–519 (2010) Kościelnik, D., Miśkowicz, M.: A clockless time-to-digital converter. Proc. IEEE Convention Elect. Electron. Eng. Israel IEEEI 2010, 516–519 (2010)
25.
go back to reference Kościelnik, D., Miśkowicz, M.: Time-to-digital converter with direct successive charge redistribution. In: Proceedings of IMEKO International Workshop on ADC Modelling, Testing and Data Converter Analysis and Design IWADC 2011, 2011 Kościelnik, D., Miśkowicz, M.: Time-to-digital converter with direct successive charge redistribution. In: Proceedings of IMEKO International Workshop on ADC Modelling, Testing and Data Converter Analysis and Design IWADC 2011, 2011
26.
go back to reference Kościelnik, D., Miśkowicz, M., Jabłeka, M.: Analysis of conversion time of time-to-digital converters with charge redistribution. Proceeding of IMEKO International Workshop on ADC Modelling, Testing and Data Converter Analysis and Design IWADC, 2011 Kościelnik, D., Miśkowicz, M., Jabłeka, M.: Analysis of conversion time of time-to-digital converters with charge redistribution. Proceeding of IMEKO International Workshop on ADC Modelling, Testing and Data Converter Analysis and Design IWADC, 2011
27.
go back to reference Allen, P.E., Holberg, D.R.: CMOS analog circuit design, 2nd edn. Oxford University Press, Oxford (2002) Allen, P.E., Holberg, D.R.: CMOS analog circuit design, 2nd edn. Oxford University Press, Oxford (2002)
28.
go back to reference Maevsky, O.V., Edel, E.A.: Converter of time intervals to code. USSR Patent 1591183, Bulletin No. 33, 070990 Maevsky, O.V., Edel, E.A.: Converter of time intervals to code. USSR Patent 1591183, Bulletin No. 33, 070990
29.
go back to reference Kinniment, D.J., Maevsky, O.V., Bystrov, A., Russell, G., Yakovlev, A.V.: On-chip structures for timing measurement and test. In: Proceeding of IEEE International Symposium Asynchronous Circuits and Systems ASYNC 2002, pp. 190–197 (2002) Kinniment, D.J., Maevsky, O.V., Bystrov, A., Russell, G., Yakovlev, A.V.: On-chip structures for timing measurement and test. In: Proceeding of IEEE International Symposium Asynchronous Circuits and Systems ASYNC 2002, pp. 190–197 (2002)
30.
go back to reference Abas, M.A., Russell, G., Kinniment, D.J.: Built-in time measurement circuits—a comparative design study. IET Comput. Digital Tech. 1(2), 87–97 (2007)CrossRef Abas, M.A., Russell, G., Kinniment, D.J.: Built-in time measurement circuits—a comparative design study. IET Comput. Digital Tech. 1(2), 87–97 (2007)CrossRef
31.
go back to reference Mantyniemi, A., Rahkonen, T., Kostamovaara, J.: A CMOS time-to-digital converter (TDC) based on a cyclic time domain successive approximation interpolation method. IEEE J. Solid-State Circ. 44(11), 3067–3078 (2009)CrossRef Mantyniemi, A., Rahkonen, T., Kostamovaara, J.: A CMOS time-to-digital converter (TDC) based on a cyclic time domain successive approximation interpolation method. IEEE J. Solid-State Circ. 44(11), 3067–3078 (2009)CrossRef
32.
go back to reference Al-Ahdab, S., Mantyniemi, A., Kostamovaara, J.: Cyclic time domain successive approximation time-to-digital converter (TDC) with sub-ps-level resolution. Proceedings of IEEE Instrumentation and Measurement Technology Conference I2MTC 2011, pp. 1–4 (2011) Al-Ahdab, S., Mantyniemi, A., Kostamovaara, J.: Cyclic time domain successive approximation time-to-digital converter (TDC) with sub-ps-level resolution. Proceedings of IEEE Instrumentation and Measurement Technology Conference I2MTC 2011, pp. 1–4 (2011)
33.
go back to reference Kazmierkowski, M.P., Malesani, L.: Current control techniques for three-phase voltage-source PWM converters: a survey. IEEE Trans. Ind. Electron. 45(5), 691–703 (1998)CrossRef Kazmierkowski, M.P., Malesani, L.: Current control techniques for three-phase voltage-source PWM converters: a survey. IEEE Trans. Ind. Electron. 45(5), 691–703 (1998)CrossRef
34.
go back to reference Malinowski, M., Jasinski, M., Kazmierkowski, M.P.: Simple direct power control of three-phase PWM rectifier using space-vector modulation (DPC-SVM). IEEE Trans. Ind. Electron. 51(2), 447–454 (2004)CrossRef Malinowski, M., Jasinski, M., Kazmierkowski, M.P.: Simple direct power control of three-phase PWM rectifier using space-vector modulation (DPC-SVM). IEEE Trans. Ind. Electron. 51(2), 447–454 (2004)CrossRef
35.
go back to reference Inose, H., Aoki, T., Watanabe, K.: Asynchronous delta modulation system. Electron. Lett. 2(3), 95–96 (1966)CrossRef Inose, H., Aoki, T., Watanabe, K.: Asynchronous delta modulation system. Electron. Lett. 2(3), 95–96 (1966)CrossRef
36.
go back to reference Kikkert, C.J., Miller, D.J.: Asynchronous delta sigma modulation, Proc. IREE 36, 83–88 (1975) Kikkert, C.J., Miller, D.J.: Asynchronous delta sigma modulation, Proc. IREE 36, 83–88 (1975)
37.
go back to reference Guan, K., Singer, A.C.: A level-crossing sampling scheme for bursty signals. Proc. Int. Conf. Inform. Sci. Syst. 3, 1357–1359 (2006) Guan, K., Singer, A.C.: A level-crossing sampling scheme for bursty signals. Proc. Int. Conf. Inform. Sci. Syst. 3, 1357–1359 (2006)
38.
go back to reference Wang, T., Wang, D., Hurst, P.J., Levy, B.C., Lewis, S.H.: A level-crossing analog-to-digital converter with triangular dither. IEEE Trans. Circ. Syst. Part I: Regul. Pap. 56(9), 2089–2099 (2009) Wang, T., Wang, D., Hurst, P.J., Levy, B.C., Lewis, S.H.: A level-crossing analog-to-digital converter with triangular dither. IEEE Trans. Circ. Syst. Part I: Regul. Pap. 56(9), 2089–2099 (2009)
39.
go back to reference Guan, K.M., Singer, A.C.: Opportunistic sampling by level-crossing. In: Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP’07), vol. 3, pp. 1513–1516, Honolulu, 2007 Guan, K.M., Singer, A.C.: Opportunistic sampling by level-crossing. In: Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP’07), vol. 3, pp. 1513–1516, Honolulu, 2007
40.
go back to reference Senay, S., Oh, J., Chaparro, L.F.: Regularized signal reconstruction for level-crossing sampling using Slepian functions. Sig. Process. 92, 1157–1165 (2012)CrossRef Senay, S., Oh, J., Chaparro, L.F.: Regularized signal reconstruction for level-crossing sampling using Slepian functions. Sig. Process. 92, 1157–1165 (2012)CrossRef
41.
go back to reference Kafashan, M., Beygi, S., Marvasti, F.: Asynchronous analog-to-digital converter based on level-crossing sampling scheme. EURASIP J. Adv. Sig. Proc., 2011, 109–117 (2011) Kafashan, M., Beygi, S., Marvasti, F.: Asynchronous analog-to-digital converter based on level-crossing sampling scheme. EURASIP J. Adv. Sig. Proc., 2011, 109–117 (2011)
42.
go back to reference Yen, J.L.: On nonuniform sampling of bandwidth-limited signals. IRE Trans. Circ. Theory CT-3, 251–257 (1956) Yen, J.L.: On nonuniform sampling of bandwidth-limited signals. IRE Trans. Circ. Theory CT-3, 251–257 (1956)
44.
go back to reference Mark, J., Todd, T.: A nonuniform sampling approach to data compression. IEEE Trans. Commun. 29(1), 24–32 (1981)CrossRef Mark, J., Todd, T.: A nonuniform sampling approach to data compression. IEEE Trans. Commun. 29(1), 24–32 (1981)CrossRef
45.
go back to reference Schell, B., Tsividis, Y.: A continuous-time ADC/DSP/DAC system with no clock and activity-dependent power dissipation. IEEE J. Solid-State Circuits 43(11), 2472–2481 (2008)CrossRef Schell, B., Tsividis, Y.: A continuous-time ADC/DSP/DAC system with no clock and activity-dependent power dissipation. IEEE J. Solid-State Circuits 43(11), 2472–2481 (2008)CrossRef
46.
go back to reference McCreary, J.L., Gray, P.R.: All-MOS charge redistribution analog-to-digital conversion techniques I. IEEE J. Solid-State Circuits 10(6), 371–379 (1975)CrossRef McCreary, J.L., Gray, P.R.: All-MOS charge redistribution analog-to-digital conversion techniques I. IEEE J. Solid-State Circuits 10(6), 371–379 (1975)CrossRef
47.
go back to reference Steele, R.: Delta Modulation Systems. Wiley, New York (1975) Steele, R.: Delta Modulation Systems. Wiley, New York (1975)
48.
go back to reference Data Converters History, in: Analog-Digital Conversion, ed. by W. Kester, Analog Devices Inc., USA, 2004 Data Converters History, in: Analog-Digital Conversion, ed. by W. Kester, Analog Devices Inc., USA, 2004
49.
go back to reference Rouse Ball, W.W., Coxeter, H.S.M.: Mathematical Recreations and Essays. Dover Publications, Thirteenth Edition (1987) Rouse Ball, W.W., Coxeter, H.S.M.: Mathematical Recreations and Essays. Dover Publications, Thirteenth Edition (1987)
50.
go back to reference Goodall, W.M.: Telephony by Pulse Code Modulation. Bell Syst. Tech. J. 26, 395–409 (1947)CrossRef Goodall, W.M.: Telephony by Pulse Code Modulation. Bell Syst. Tech. J. 26, 395–409 (1947)CrossRef
51.
go back to reference Bernard M. Gordon and Robert P. Talambiras, Signal Conversion Apparatus. U.S. Patent 3,108,266 Bernard M. Gordon and Robert P. Talambiras, Signal Conversion Apparatus. U.S. Patent 3,108,266
52.
go back to reference C.W. Barbour, Simplified PCM Analog-to-Digital Converters Using Capacity Charge Transfer. In: Proceedings National Telemetering Conference, pp. 4.1–4.11. Chicago, 1961 C.W. Barbour, Simplified PCM Analog-to-Digital Converters Using Capacity Charge Transfer. In: Proceedings National Telemetering Conference, pp. 4.1–4.11. Chicago, 1961
53.
go back to reference T. Kugelstadt, The Operation of the SAR-ADC Based on Charge Redistribution, Texas Instruments Analog Applications Journal, pp. 10–12, Feb. 2000 T. Kugelstadt, The Operation of the SAR-ADC Based on Charge Redistribution, Texas Instruments Analog Applications Journal, pp. 10–12, Feb. 2000
54.
go back to reference Scott, M.D., Boser, B.E., Pister, K.S.J.: An ultra low-energy ADC for smart dust. IEEE J. Solid-State Circuits 38(7), 1123–1129 (2003)CrossRef Scott, M.D., Boser, B.E., Pister, K.S.J.: An ultra low-energy ADC for smart dust. IEEE J. Solid-State Circuits 38(7), 1123–1129 (2003)CrossRef
55.
go back to reference Hong, H., Lee, G.: A 65fJ/conversion-step 0.9-V 200-kS/s rail-to-rail 8-bit successive approximation ADC. IEEE J. Solid-State Circuits 42(10), 2161–2168 (2007)CrossRef Hong, H., Lee, G.: A 65fJ/conversion-step 0.9-V 200-kS/s rail-to-rail 8-bit successive approximation ADC. IEEE J. Solid-State Circuits 42(10), 2161–2168 (2007)CrossRef
56.
go back to reference B.P. Ginsburg and A.P. Chandrakasan, An energy-efficient charge recycling approach for a SAR converter with capacitive DAC. In: Proceedings of the IEEE ISCAS, pp. 184–187, 2005 B.P. Ginsburg and A.P. Chandrakasan, An energy-efficient charge recycling approach for a SAR converter with capacitive DAC. In: Proceedings of the IEEE ISCAS, pp. 184–187, 2005
57.
go back to reference R.Y.-K. Choi and C.-Y. Tsui, A low energy two-step successive approximation algorithm for ADC design. In: Proceedings of the IEEE ISQED, pp. 317–320, 2008 R.Y.-K. Choi and C.-Y. Tsui, A low energy two-step successive approximation algorithm for ADC design. In: Proceedings of the IEEE ISQED, pp. 317–320, 2008
58.
go back to reference Saberi, M., Lotfi, R., Mafinezhad, K., Serdijn, W.A.: Analysis of Power Consumption and Linearity in Capacitive Digital-to-Analog Converters Used in Successive Approximation ADCs, pp. 1736–1748. IEEE Trans. Circuits Syst. I, Regular Papers (2011) Saberi, M., Lotfi, R., Mafinezhad, K., Serdijn, W.A.: Analysis of Power Consumption and Linearity in Capacitive Digital-to-Analog Converters Used in Successive Approximation ADCs, pp. 1736–1748. IEEE Trans. Circuits Syst. I, Regular Papers (2011)
59.
go back to reference K.-Y. Khoo and A. Willson, Charge Recovery on a Databus. In: Proceedings of the International Symposium on Low Power Electrical and Design, pp. 185–189, 1995 K.-Y. Khoo and A. Willson, Charge Recovery on a Databus. In: Proceedings of the International Symposium on Low Power Electrical and Design, pp. 185–189, 1995
60.
go back to reference Brian P. Ginsburg and Anantha P. Chandrakasan, 500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC, IEEE J. Solid-State Circ., 42(4) (2007) Brian P. Ginsburg and Anantha P. Chandrakasan, 500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC, IEEE J. Solid-State Circ., 42(4) (2007)
61.
go back to reference M.F. Tompsett, Semiconductor charge-coupled device analog-to-digital converter. U.S. Patent 4136335, 1979 M.F. Tompsett, Semiconductor charge-coupled device analog-to-digital converter. U.S. Patent 4136335, 1979
62.
go back to reference Paul E. Green, Charge domain successive approximation analog to digital converter. Patent US 5010340 Paul E. Green, Charge domain successive approximation analog to digital converter. Patent US 5010340
63.
go back to reference Kyung, C.M., Kim, C.K.: Pipeline analog-to-digital conversion with charge-coupled devices. IEEE J. Solid-State Circuits 15, 255–257 (1980)CrossRef Kyung, C.M., Kim, C.K.: Pipeline analog-to-digital conversion with charge-coupled devices. IEEE J. Solid-State Circuits 15, 255–257 (1980)CrossRef
64.
go back to reference Kyung, C.M., Kim, C.K.: Charged-coupled analog-to-digital converter. IEEE J. Solid-State Circ. 16(6), 621–626 (1981)CrossRef Kyung, C.M., Kim, C.K.: Charged-coupled analog-to-digital converter. IEEE J. Solid-State Circ. 16(6), 621–626 (1981)CrossRef
65.
go back to reference D. Kościelnik, M. Miśkowicz, Method and apparatus for analog-to-digital conversion using asynchronous Sigma-Delta modulation. U.S. Patent 7948413, 2011 D. Kościelnik, M. Miśkowicz, Method and apparatus for analog-to-digital conversion using asynchronous Sigma-Delta modulation. U.S. Patent 7948413, 2011
66.
go back to reference Roza, E.: Analog-to-digital conversion via duty-cycle modulation. IEEE Trans. Circ. Syst. II 44, 907–914 (1997)CrossRef Roza, E.: Analog-to-digital conversion via duty-cycle modulation. IEEE Trans. Circ. Syst. II 44, 907–914 (1997)CrossRef
67.
go back to reference Sayiner, N., Sorensen, H.N., Viswanathan, T.R.: A level-crossing sampling scheme for A/D conversion. IEEE Trans. Circ. Syst. II 43, 335–339 (1996)CrossRef Sayiner, N., Sorensen, H.N., Viswanathan, T.R.: A level-crossing sampling scheme for A/D conversion. IEEE Trans. Circ. Syst. II 43, 335–339 (1996)CrossRef
68.
go back to reference D. Kościelnik, M. Miśkowicz, Modeling event-driven successive charge redistribution in ADC with varying rate of charge transfer. In: Proceeding of IEEE Convention of Electrical and Electronics Engineers in Israel IEEEI 2012, 2012 D. Kościelnik, M. Miśkowicz, Modeling event-driven successive charge redistribution in ADC with varying rate of charge transfer. In: Proceeding of IEEE Convention of Electrical and Electronics Engineers in Israel IEEEI 2012, 2012
69.
go back to reference Kościelnik, D., Miśkowicz, M.: Time-to-digital converters based on event-driven successive charge redistribution: a theoretical approach. Measurement 45, 2511–2528 (2012)CrossRef Kościelnik, D., Miśkowicz, M.: Time-to-digital converters based on event-driven successive charge redistribution: a theoretical approach. Measurement 45, 2511–2528 (2012)CrossRef
Metadata
Title
Event-Driven Successive Charge Redistribution Schemes for Clockless Analog-to-Digital Conversion
Authors
Dariusz Kościelnik
Marek Miśkowicz
Copyright Year
2014
Publisher
Springer Berlin Heidelberg
DOI
https://doi.org/10.1007/978-3-642-39655-7_6