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Computing

Exploring and optimizing partitioning of large designs for multi-FPGA based prototyping platforms

  • 21-07-2020
  • Regular Paper
Published in:
Authors
Umer Farooq
Bander A. Alzahrani
Published in
Computing | Issue 11/2020

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Abstract

Recently, multi-FPGA platforms have become a popular choice to prototype complex digital systems. This is because of unique advantages such as high frequency and real world testing experience that are offered when compared to other pre-silicon testing techniques. However, one of several challenges faced by multi-FPGA prototyping is the requirement of an efficient back end flow. Partitioning is a key part of the back end flow of multi-FPGA systems and it directly affects the quality of final prototyped design. In this work, we explore two different partitioning approaches: one is multilevel; while the other is hierarchical partitioning approach. For experimentation, we use a suite of fourteen large benchmarks. Experimental results reveal that the multilevel approach gives 12.5% better frequency results for mono-cluster benchmarks while the hierarchical approach gives 13% better results for multi-cluster benchmarks. Furthermore, the hierarchical approach requires, on average, 60% less execution time when compared to the multilevel partitioning approach.

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Title
Exploring and optimizing partitioning of large designs for multi-FPGA based prototyping platforms
Authors
Umer Farooq
Bander A. Alzahrani
Publication date
21-07-2020
Publisher
Springer Vienna
Published in
Computing / Issue 11/2020
Print ISSN: 0010-485X
Electronic ISSN: 1436-5057
DOI
https://doi.org/10.1007/s00607-020-00834-5
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