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2020 | OriginalPaper | Chapter

Extensible and Configurable RISC-V Based Virtual Prototype

Authors : Vladimir Herdt, Daniel Große, Hoang M. Le, Rolf Drechsler

Published in: Languages, Design Methods, and Tools for Electronic System Design

Publisher: Springer International Publishing

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Abstract

Internet-of-Things (IoT) opens a new world of possibilities for both personal and industrial applications. At the heart of an IoT device, the processor is the core component. Hence, as an open and free instruction set architecture RISC-V is gaining huge popularity for IoT. A large ecosystem is available around RISC-V, including various RTL implementations at one end and high-speed instruction set simulators (ISSs) at the other end. These ISSs facilitate functional verification of RTL implementations as well as early SW development to some extent. However, being designed predominantly for speed, they can hardly be extended to support further system-level use cases such as design space exploration, power/timing/performance validation, or analysis of complex HW/SW interactions. In this paper, we propose and implement the first RISC-V based Virtual Prototype (VP) with the goal of filling this gap. We provide a RISC-V RV32IM core, a PLIC-based interrupt controller, and an essential set of peripherals together with SW debug capabilities. The VP is designed as extensible and configurable platform with a generic bus system and implemented in standard-compliant SystemC and TLM-2.0. The latter point is very important, since it allows to leverage cutting-edge SystemC-based modeling techniques needed for the mentioned use cases. Our VP allows a significantly faster simulation compared to RTL, while being more accurate than existing ISSs. Finally, our RISC-V VP is fully open source to help expanding the RISC-V ecosystem and stimulating further research and development.
Footnotes
2
Support for integration with the C/C++ library is also available, e.g., by executing the instructions at the beginning of the main function or integrating them directly into the crt0.S file, which is the entry point of the C library and similarly to the bare-metal code also calls the main function after performing some basic initialization tasks.
 
3
Example based on the newlib port https://​github.​com/​riscv/​riscv-newlib.
 
4
It is also possible to execute a trap handler, similar to the interrupt handler described in the previous section (e.g., essentially, jump to the level-0 interrupt handler with the mcause CSR being set to a syscall number), and then redirect the write to e.g. a terminal component.
 
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Metadata
Title
Extensible and Configurable RISC-V Based Virtual Prototype
Authors
Vladimir Herdt
Daniel Große
Hoang M. Le
Rolf Drechsler
Copyright Year
2020
DOI
https://doi.org/10.1007/978-3-030-31585-6_7