Fast and simple model generation for superjunction power MOSFETs

Today, modern switched power electronic systems can be found in a variety of applications such as AC adapters, solar inverters, battery chargers, variable frequency motor drives, etc. They include modern power semiconductor switches which are increasingly based on superjunction techniques, silicon carbide (SiC) or gallium nitride (GaN) semiconductors. In simulations, it is becoming increasingly important to better represent the high-frequency behavior of MOSFETs. This makes it possible, for example, to take a closer look at control problems caused by strong load changes or to simulate the conducted electromagnetic emissions of an electronic system. In [1] it is described that one of the main challenges for accurate electromagnetic emission simulations is that the generated noise in a power electronic system is highly dependent on the circuit and semiconductor parasitics.

For accurate SPICE simulations in power electronics, accurate models of power MOSFETs are therefore essential. In many cases, manufacturers do not provide such models at all, or not for common SPICE simulators like LTspice. Manufacturer models are also mostly analytical models which are based on precise physical knowledge of the internal structure, like shown in [2]. To generate such models without this knowledge, so-called behavioral models are commonly used [3‐5].

This paper shows how behavioral models for SPICE simulation can be created using a simple measurement with a vector network analyzer (VNA). A special focus is put on modeling the voltage-dependent parasitic capacitances¹ of superjunction (SJ) MOSFETs since they are highly nonlinear and therefore difficult to impossible to model with somewhat not too complex mathematical equations. While accurate modeling of these nonlinearities is important for the accuracy of the models [6], it often leads to long simulation times and frequent convergence problems. This paper shows a way to generate fast and well converging models using an SJ MOSFET with very strong nonlinear parasitic capacitances. As gallium nitride (GaN) and silicon carbide (SiC) power transistors show less steep voltage dependent capacitances, we believe the model is also suited for those devices. The measurement procedure described in Sect. 2 also showed results for GaN and SiC devices that were consistent with the data sheet. For such models, however, the modeling of the output- and reverse-diode characteristic curve described in Sect. 3 must be revised. For example, GaN devices do not have an inherent body diode but are still capable of reverse conduction.

As described in [7], all parasitic capacitances and inductances required for a behavioral model of a power MOSFET with three pins can be determined by a single S-parameter measurement using a VNA. The measuring system shown in Fig. 1, which is described in great detail in [8], additionally offers the possibility to measure these parasitic capacitances voltage dependent. The power MOSFET is depicted with all parasitics. These include the voltage-dependent parasitic capacitances \(C_{GD}\), \(C_{GS}\) and \(C_{DS}\) as well as parasitic terminal inductances of the bonding wires \(L_{G}\), \(L_{D}\) and \(L_{S}\). The VNA is protected by two DC blocks from the high voltage source \(V_{DS}\). The HF-filters prevent the measurement from being influenced by \(V_{DS}\) which is stepped over the first 100 V in 1 V steps. From the obtained voltage-dependent S-parameters, the parasitic inductances as well as the voltage-dependent capacities can be calculated in one single step. The extraction of the capacitances from the S-parameter measurements can be done at any frequency below the resonant frequency; the extraction of the inductances at any frequency above the resonant frequency. Secondary effects such as temperature or frequency dependence of the parasitics were thoroughly tested and can be excluded. Likewise, no significant fabrication tolerances could be determined by measurements on various components although such tolerances are not ruled out. For this specific power MOSFET, the S-parameters were sampled at a frequency of 10 MHz to calculate the capacitances because the S-parameter measurement was most accurate over the whole drain-source voltage range there. In a similar way, as it is described in [7], the equations (2) and (3) show this calculation using the drain-source capacitance as an example. The parasitic inductances are sampled at 1 GHz and are calculated similarly. These values are constant and amount to \(L_{D}={0.2}\) nH, \(L_{G}={3.5}\) nH and \(L_{S}={1}\) nH for the given model.

Figure 2 shows the result of the measurements of the voltage-dependent input (\(C_{iss}\)), output (\(C_{oss}\)) and reverse transfer (\(C_{rss}\)) capacitances in comparison with the data sheet up to a drain-source voltage of 100 V, above which the values do not change significantly anymore. These capacitances are defined in terms of the equivalent circuit capacitances as: where \(C_{GS}\) is referred to the capacitance due to the overlap of the source and the channel regions by the polysilicon gate and is more or less independent of the applied drain source voltage (\(V_{DS}\)).

\(C_{GD}\) often consists of two parts. The first part of this capacitance is defined by the overlap of the gate (e.g. polysilicon) and the semiconductor material underneath in the drift region. The second part is associated with the depletion region under the gate. \(C_{GD}\) is a nonlinear function of the drain-source voltage.

\(C_{DS}\) is the capacitance associated with the body diode and strongly depends on the drain-source voltage.

The difference in the measured values of the reverse transfer capacitance \(C_{rss}\) in Fig. 2 can be attributed to the insufficient measuring dynamics of the VNA used for the measurement. The measurement dynamics of a more modern VNA would be sufficient to measure this capacitance more accurately. However, as shown in Sect. 4, it turns out that these differences do not have a great influence on the resulting model. The small deviation of \(C_{rss}\) from the data sheet values at approx. 25 V was confirmed by several measurements of different components of the same type. Furthermore, a linear extrapolation seems to be sufficient for all capacitance values above 100 V.

Almost the entire model can be represented by voltage controlled current sources which provide several advantages compared to the models that are usually provided by the IC manufacturers. The entire model is shown in Fig. 3. In the following, modeling of the individual components is described.

This paper shows an approach to simulate behavioral models of power MOSFETs with very strong nonlinear parasitic capacitances, particularly superjunction power MOSFETs. In combination with a simple measurement setup using a VNA, this new modeling method is possible without detailed knowledge of the internal structure of the MOSFET and its parasitics. With the obtained measurement results from the VNA, the nonlinear capacitances can be easily transferred into the SPICE model which makes it possible to automate the modeling process. By comparison with the manufacturer’s simulation model, it was shown that the approach of modeling with voltage controlled current sources shows promising results. As has been shown, certain manufacturer models only work in a narrow range with regard to the set simulation parameters. The proposed model tends to give better convergence in less simulation time and fewer simulation errors without requiring special settings in SPICE. Further performance tests regarding simulation time and convergence in more complex circuits are planned.