FPGA Based Implementation of Hamming Encoder and Decoder

Communication is among the vast and fast-growing engineering fields. Improving communication efficiency by overcoming external electromagnetic and noise sources is a difficult task. Different methods for detecting and resolving errors are implemented to reduce data loss during transmission. A novel approach that uses cyclic redundancy tests is proposed in this paper. In the field of communication, there have been many developments in the digital world. In most fields of communication, the input message or data is encoded and transmitted through a medium of transmission. Data are obtained at the receiver and the original data is successfully retrieved after decoding the received data. The paper aims to explain the hammer code design cycle with VLSI, as FPGA is cheaper than the other device. The hamming algorithm for encoding and decoding was discussed in this paper and the results were obtained by implementing hamming error detection and the correction code. Compared to the traditional Narayanan and Ramesh (Journal of Engineering and Applied Sciences 12:6281–6285, 2017 [1]) hamming parity checking process, hamming code is an improved version and used in Verilog to transmit n-bit information with redundancy bits. A hamming to find out how important these redundant bits.