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Published in:
2012 | OriginalPaper | Chapter
FPGA Design and Implementation of Low Power Consumption LDPC Encoder Based on DVB-S2
Authors : Xingyu Zou, Hui Qian, Shuying Cheng
Published in: Advances in Computer, Communication, Control and Automation
Publisher: Springer Berlin Heidelberg
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According to DVB-S2 standard for LDPC (Low Density Parity Check) codes, a novel LDPC codes encoder circuit structure is designed. The design has been implemented on the FPGA (Filed Programmable Gate Array). Simulations results show that, due to the random nature of the input data, this structure significantly reduces the power consumption of the calculation circuit. Meanwhile, during the entire coding process, the data is processed parallelly and distributed storage so that we can not only enhance the information processing rate but also save storage space in FPGA.