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2014 | OriginalPaper | Chapter

8. Hardware Accelerator for Feature Point Detection and Matching

Authors : Jun-Seok Park, Lee-Sup Kim

Published in: Algorithm & SoC Design for Automotive Vision Systems

Publisher: Springer Netherlands

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Abstract

Recently, many vehicle manufacturers have adopted a vision processing based driver assistance system (DAS) for safety. Since vehicles cannot allow any crash or collision even when running very fast, all vision algorithms should be operated in real-time without any error. Since many algorithms such as object recognition/tracking, image matching, and simultaneous localization and mapping (SLAM) are based on the interest point detection and matching algorithm, interest point detection and matching algorithms should be accelerated to provide result data for overall vision system in real-time. However, they are one of the most compute-intensive operations in DAS and even the state-of-the-art hardwired accelerators hardly achieve 60 frames per second (fps) only in VGA resolution (640 × 480). They suffer from tremendous hardware overhead because they are implemented based on heterogeneous many-core system. To overcome these limitations, we aims to implement hardware which achieve more than 90 frames per second in full HD resolution (1080p) only with 30 % of logic gates compared to the state-of-the-art object recognition processors. In this chapter, we introduces three techniques to design this hardware : (1) Joint algorithm-architecture optimizations for exploiting bit-level parallelism, (2) A low-power unified hardware platform for interest point detection and matching, and (3) scalable hardware architecture.

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Footnotes
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Metadata
Title
Hardware Accelerator for Feature Point Detection and Matching
Authors
Jun-Seok Park
Lee-Sup Kim
Copyright Year
2014
Publisher
Springer Netherlands
Book
Algorithm & SoC Design for Automotive Vision Systems

Print ISBN: 978-94-017-9074-1

Electronic ISBN: 978-94-017-9075-8

Copyright Year: 2014

DOI
https://doi.org/10.1007/978-94-017-9075-8_8