Skip to main content
Top

2014 | OriginalPaper | Chapter

Hardware-Based Computational Intelligence for Size, Weight, and Power Constrained Environments

Authors : Bryant Wysocki, Nathan McDonald, Clare Thiem, Garrett Rose, Mario Gomez II

Published in: Network Science and Cybersecurity

Publisher: Springer New York

Activate our intelligent search to find suitable subject content or patents.

search-config
loading …

Abstract

Nanotechnology research is an enabling field and is closely aligned with advances in neuromorphic architectures, energy efficient computing, and autonomy efforts. The development of neuromorphic circuits leverages a mixture of proven CMOS technologies with experimental devices and architectures that pose significant challenges for integration and fabrication. This chapter examines the pressures pushing the development of unconventional computing designs for size, weight, and power constrained environments and briefly reviews some of the trends that are influencing the development of solid-state neuromorphic systems. Later sections provide high level examples of selected approaches to hardware design and fabrication.

Dont have a licence yet? Then find out more about our products and how to get one now:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

  • über 102.000 Bücher
  • über 537 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Maschinenbau + Werkstoffe
  • Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 390 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Maschinenbau + Werkstoffe




 

Jetzt Wissensvorsprung sichern!

Springer Professional "Wirtschaft"

Online-Abonnement

Mit Springer Professional "Wirtschaft" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 340 Zeitschriften

aus folgenden Fachgebieten:

  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Versicherung + Risiko




Jetzt Wissensvorsprung sichern!

Literature
1.
go back to reference P.W. Singer, Wired for War: The Robotics Revolution and Conflict in the 21st Century (Penguin, New York, 2009) P.W. Singer, Wired for War: The Robotics Revolution and Conflict in the 21st Century (Penguin, New York, 2009)
3.
go back to reference J. Misra, I. Saha, Artificial neural networks in hardware: a survey of two decades of progress, J. Neurocomput. 74, 239–255 (2010) J. Misra, I. Saha, Artificial neural networks in hardware: a survey of two decades of progress, J. Neurocomput. 74, 239–255 (2010)
5.
go back to reference M.D. Hill, M.R. Marty, Amdahl’s law in the multicore era. Computer 41(7), 33–38 (2008)CrossRef M.D. Hill, M.R. Marty, Amdahl’s law in the multicore era. Computer 41(7), 33–38 (2008)CrossRef
6.
go back to reference H. Esmaeilzadeh, E. Blem, R.S. Amant, K. Sankaralingam, D. Burger, Dark silicon and the end of multicore scaling, in 38th Annual International Symposium on Computer Architecture (ISCA), pp. 365–376, 4–8 June 2011 H. Esmaeilzadeh, E. Blem, R.S. Amant, K. Sankaralingam, D. Burger, Dark silicon and the end of multicore scaling, in 38th Annual International Symposium on Computer Architecture (ISCA), pp. 365–376, 4–8 June 2011
7.
go back to reference P.M. Kogge, Hardware Evolution Trends of Extreme Scale Computing, University of Notre Dame, 26 April 2011 P.M. Kogge, Hardware Evolution Trends of Extreme Scale Computing, University of Notre Dame, 26 April 2011
8.
go back to reference J. Koomey, Growth in Data Center Electricity use 2005 to 2010 Analytics Press, Oakland (2011) J. Koomey, Growth in Data Center Electricity use 2005 to 2010 Analytics Press, Oakland (2011)
11.
go back to reference G. Snider, Prolog: Memristor Minds, in Advances in Neuromorphic Memristor Science and Applications, Springer Series in Cognitive And Neural Systems 4, ed. by R. Kozma, R. Pino, G. Pazienza (Springer, New York, 2012), pp. 3–7CrossRef G. Snider, Prolog: Memristor Minds, in Advances in Neuromorphic Memristor Science and Applications, Springer Series in Cognitive And Neural Systems 4, ed. by R. Kozma, R. Pino, G. Pazienza (Springer, New York, 2012), pp. 3–7CrossRef
12.
go back to reference H. Ames, M. Versace et al., Persuading Computers to Act More Like Brains, in Advances in Neuromorphic Memristor Science and Applications, Springer Series in Cognitive and Neural Systems 4, ed. by R. Kozma, R. Pino, G. Pazienza (Springer, New York, 2012), pp. 37–61CrossRef H. Ames, M. Versace et al., Persuading Computers to Act More Like Brains, in Advances in Neuromorphic Memristor Science and Applications, Springer Series in Cognitive and Neural Systems 4, ed. by R. Kozma, R. Pino, G. Pazienza (Springer, New York, 2012), pp. 37–61CrossRef
13.
go back to reference C. Yakopcic, T.M. Taha et al., Analysis of a memristor based 1T1M crossbar architecture, in The 2011 International Joint Conference on Neural Networks (IJCNN), IEEE, pp. 3243–3247 (2011) C. Yakopcic, T.M. Taha et al., Analysis of a memristor based 1T1M crossbar architecture, in The 2011 International Joint Conference on Neural Networks (IJCNN), IEEE, pp. 3243–3247 (2011)
14.
go back to reference D.B. Strukov, K.K. Likharev, Reconfigurable Nano-Crossbar Architectures, in Nanoelectronics and Information Technology, 3rd edn., ed. by R. Waser (Wiley, New York, 2012), pp. 543–562 D.B. Strukov, K.K. Likharev, Reconfigurable Nano-Crossbar Architectures, in Nanoelectronics and Information Technology, 3rd edn., ed. by R. Waser (Wiley, New York, 2012), pp. 543–562
15.
go back to reference GS. Rose, H. Manem et al., Leveraging memristive systems in the construction of digital logic circuits and architectures, in Proceedings of the IEEE , 100(6), 2033–2049 (2012) GS. Rose, H. Manem et al., Leveraging memristive systems in the construction of digital logic circuits and architectures, in Proceedings of the IEEE , 100(6), 2033–2049 (2012)
16.
go back to reference J. Rajendran, H. Manem et al., An energy-efficient memristive threshold logic circuit. IEEE. Trans. Comput. 61(4), 6:1–6:22 (2012)MathSciNetCrossRef J. Rajendran, H. Manem et al., An energy-efficient memristive threshold logic circuit. IEEE. Trans. Comput. 61(4), 6:1–6:22 (2012)MathSciNetCrossRef
17.
go back to reference J. Rajendran, H. Manem et al., An approach to tolerate variations for memristor based applications, in Proceedings of the 24th International Conference on VLSI Design (VLSI Design) pp. 18–23 (2011) J. Rajendran, H. Manem et al., An approach to tolerate variations for memristor based applications, in Proceedings of the 24th International Conference on VLSI Design (VLSI Design) pp. 18–23 (2011)
18.
go back to reference J. Rajendran, H. Manem et al., Memristor based programmable threshold logic array, in IEEE/ACM International Symposium on Nanoscale Architectures, pp. 5–10 (2010) J. Rajendran, H. Manem et al., Memristor based programmable threshold logic array, in IEEE/ACM International Symposium on Nanoscale Architectures, pp. 5–10 (2010)
19.
go back to reference J. Rajendran, R. Karri, G.S. Rose, Parallel memristors improve variation tolerance in memristive digital circuits, in IEEE International Symposium on Circuits and Systems. pp. 2241–2244 (2011) J. Rajendran, R. Karri, G.S. Rose, Parallel memristors improve variation tolerance in memristive digital circuits, in IEEE International Symposium on Circuits and Systems. pp. 2241–2244 (2011)
20.
go back to reference H. Manem, G.S. Rose, Design considerations for variation tolerant multilevel cmos/nano memristor memory, in ACM Great Lakes Symposium on VLSI. pp. 287–292 (2010) H. Manem, G.S. Rose, Design considerations for variation tolerant multilevel cmos/nano memristor memory, in ACM Great Lakes Symposium on VLSI. pp. 287–292 (2010)
21.
go back to reference H. Manem, G.S. Rose, A Crosstalk Minimization technique for sublithographic programmable logic arrays, in IEEE Conference on Nanotechnology. pp. 218–222 (2009) H. Manem, G.S. Rose, A Crosstalk Minimization technique for sublithographic programmable logic arrays, in IEEE Conference on Nanotechnology. pp. 218–222 (2009)
22.
go back to reference H. Manem, J. Rajendran, G.S. Rose, Design Considerations for Multi-Level CMOS/Nano Memristive Memory. ACM. J. Emerg. Technol. Comput. Syst. 8(1), 1–22 (2012)CrossRef H. Manem, J. Rajendran, G.S. Rose, Design Considerations for Multi-Level CMOS/Nano Memristive Memory. ACM. J. Emerg. Technol. Comput. Syst. 8(1), 1–22 (2012)CrossRef
23.
go back to reference H. Manem, G.S. Rose, A read-monitored write circuit for 1T1 M memristor memories, IEEE International Symposium on Circuits and Systems. pp. 2938–2941 (2011) H. Manem, G.S. Rose, A read-monitored write circuit for 1T1 M memristor memories, IEEE International Symposium on Circuits and Systems. pp. 2938–2941 (2011)
24.
go back to reference M. Soltiz, C. Merkel et al., RRAM-based adaptive neural logic block for implementing non-linearly separable functions, in Proceedings of IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) (2012) M. Soltiz, C. Merkel et al., RRAM-based adaptive neural logic block for implementing non-linearly separable functions, in Proceedings of IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) (2012)
25.
go back to reference M. Solti, D. Kudithipudi et al., Submitted 2012. Single-Layer Neural Logic Blocks Using Memristive Synapses, Submitted to IEEE Transaction on Computers (2012) M. Solti, D. Kudithipudi et al., Submitted 2012. Single-Layer Neural Logic Blocks Using Memristive Synapses, Submitted to IEEE Transaction on Computers (2012)
26.
go back to reference H. Manem, J. Rajendran, G.S. Rose, Stochastic gradient descent inspired training technique for a hybrid CMOS/Nano trainable threshold gate array. IEEE. Trans. Circuits. Syst. 59(5), 1051–1060 (2012)MathSciNetCrossRef H. Manem, J. Rajendran, G.S. Rose, Stochastic gradient descent inspired training technique for a hybrid CMOS/Nano trainable threshold gate array. IEEE. Trans. Circuits. Syst. 59(5), 1051–1060 (2012)MathSciNetCrossRef
27.
go back to reference A.R. Omondi, J.C. Rajapakse, FPGA Implementations of Neural Networks (Springer, Netherlands, 2006)CrossRef A.R. Omondi, J.C. Rajapakse, FPGA Implementations of Neural Networks (Springer, Netherlands, 2006)CrossRef
28.
go back to reference A. Eide, T. Lindblad et al., An implementation of the zero instruction set computer (ZISC036) on a PC/ISA-bus card, in 1994 WNN/FNN (1994) A. Eide, T. Lindblad et al., An implementation of the zero instruction set computer (ZISC036) on a PC/ISA-bus card, in 1994 WNN/FNN (1994)
29.
go back to reference F.M. Dias, A. Antunes, A. Mota, Artificial Neural Networks: a Review of Commercial Hardware. Eng. Appl. Artif. Intell. IFAC 17(8), 945–952 (2004)CrossRef F.M. Dias, A. Antunes, A. Mota, Artificial Neural Networks: a Review of Commercial Hardware. Eng. Appl. Artif. Intell. IFAC 17(8), 945–952 (2004)CrossRef
32.
go back to reference Y. Q. Liu, D. Wei, N. Zhang, M.Z. Zhao Vehicle-license-plate recognition based on neural networks, in Information and Automation (ICIA), 2011 IEEE International Conference on, pp. 363–366 (2011) Y. Q. Liu, D. Wei, N. Zhang, M.Z. Zhao Vehicle-license-plate recognition based on neural networks, in Information and Automation (ICIA), 2011 IEEE International Conference on, pp. 363–366 (2011)
33.
go back to reference K. Shen, C.I. Bargmann, The immunoglobin superfamily protein SYG-1 determines the location of specific synapses in C. Elegans. In Cell. 112(5), 619–630 (2003)CrossRef K. Shen, C.I. Bargmann, The immunoglobin superfamily protein SYG-1 determines the location of specific synapses in C. Elegans. In Cell. 112(5), 619–630 (2003)CrossRef
34.
go back to reference K. Diefendorff, P.K. Dubey, How multimedia workloads will change processor design. In Computer 30(9), 43–45 (1997)CrossRef K. Diefendorff, P.K. Dubey, How multimedia workloads will change processor design. In Computer 30(9), 43–45 (1997)CrossRef
35.
go back to reference R.E. Pino, G. Genello et al., Emerging neuromorphic computing architectures and enabling hardware for cognitive information processing applications. Air Force Research Lab Rome, Information Directorate (2010) R.E. Pino, G. Genello et al., Emerging neuromorphic computing architectures and enabling hardware for cognitive information processing applications. Air Force Research Lab Rome, Information Directorate (2010)
36.
go back to reference D. Shires, S.J. Park et al., Asymmetric core computing for US Army high-performance computing applications (No. ARL-TR-4788). Army Research Lab Aberdeen Proving Ground MD, Computational and Information Sciences Dir (2009) D. Shires, S.J. Park et al., Asymmetric core computing for US Army high-performance computing applications (No. ARL-TR-4788). Army Research Lab Aberdeen Proving Ground MD, Computational and Information Sciences Dir (2009)
37.
go back to reference B. Barney, Introduction to parallel computing. Lawrence. Livermore. Nat. Lab. 6(13), 10 (2010) B. Barney, Introduction to parallel computing. Lawrence. Livermore. Nat. Lab. 6(13), 10 (2010)
38.
go back to reference R. Zbikowski, Fly like a fly [micro-air vehicle], in Spectrum, IEEE 42(11), pp. 46–51 (2005) R. Zbikowski, Fly like a fly [micro-air vehicle], in Spectrum, IEEE 42(11), pp. 46–51 (2005)
Metadata
Title
Hardware-Based Computational Intelligence for Size, Weight, and Power Constrained Environments
Authors
Bryant Wysocki
Nathan McDonald
Clare Thiem
Garrett Rose
Mario Gomez II
Copyright Year
2014
Publisher
Springer New York
DOI
https://doi.org/10.1007/978-1-4614-7597-2_9

Premium Partner