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Telecommunication Systems
Published in: Telecommunication Systems 4/2018

11-12-2017

Hardware implementation of fault tolerance NoC core mapping

Authors: Naresh Kumar Reddy Beechu, Vasantha Moodabettu Harishchandra, Nithin Kumar Yernad Balachandra

Published in: Telecommunication Systems | Issue 4/2018

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Abstract

Due to performance and reliability, network on chip (NoC) is considered to be the future generation interconnect technique for multiple cores in a chip. This paper proposes a system level core mapping technique which improves the performance of the whole system, while rectifying the temporary faults and permanent faults in the system using error correcting codes and spare core. This technique mainly focuses on the core mapping and faults on the system. This results in reliable core mapping and improved performance when a fault-related error occurs on an NoC. At last, the proposed core mapping technique is simulated and verified on FPGA board (Kintex-7 FPGA KC705 Evaluation Kit).
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Metadata
Title
Hardware implementation of fault tolerance NoC core mapping
Authors
Naresh Kumar Reddy Beechu
Vasantha Moodabettu Harishchandra
Nithin Kumar Yernad Balachandra
Publication date
11-12-2017
Publisher
Springer US
Published in
Telecommunication Systems / Issue 4/2018
Print ISSN: 1018-4864
Electronic ISSN: 1572-9451
DOI
https://doi.org/10.1007/s11235-017-0412-2

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