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16-06-2024

Hermite Expansion Technique for Model Reduction of Circuit Systems with Delay Components

Authors: Zhi-Yong Qiu, Zhen-Hua Guo, Yao-Lin Jiang, Ya-Qian Zhao, Ren-Gang Li

Published in: Circuits, Systems, and Signal Processing | Issue 9/2024

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Abstract

Model order reduction technique provides an effective way to reduce computational complexity in large-scale circuit simulations. This paper proposes a new model order reduction method for delay circuit systems based on Hermite expansion technique. The presented method consists of three steps i.e., first the delay elements are approximated using the recursive relation of Hermite polynomials, then in the second step, the reduced order is estimated for the delay circuit system using a delay truncation in the Hermite domain and in the third step, a multi-order Arnoldi process is computed for obtaining the projection matrix. In the following, the reduced order delay circuit model is obtained by the projection matrix. Moment matching and passivity properties of the reduced circuit system are also analyzed. Two circuit examples with delay components are performed to verify the effectiveness of the proposed MOR approach.

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Literature
1.
go back to reference R. Achar, Modeling of high-speed interconnects for signal integrity analysis: Part I. IEEE Microw. Mag. 12(5), 61–74 (2011)MathSciNetCrossRef R. Achar, Modeling of high-speed interconnects for signal integrity analysis: Part I. IEEE Microw. Mag. 12(5), 61–74 (2011)MathSciNetCrossRef
2.
go back to reference R. Achar, M.S. Nakhla, Simulation of high-speed interconnects. Proc. IEEE 89(5), 693–728 (2001)CrossRef R. Achar, M.S. Nakhla, Simulation of high-speed interconnects. Proc. IEEE 89(5), 693–728 (2001)CrossRef
3.
go back to reference N. Ahamad, A. Sikander, A novel approach of order diminution using time moment concept with Routharray and salp swarm algorithm. Turk. J. Electr. Eng. Comput. Sci. 29(2), 1077–1091 (2021)CrossRef N. Ahamad, A. Sikander, A novel approach of order diminution using time moment concept with Routharray and salp swarm algorithm. Turk. J. Electr. Eng. Comput. Sci. 29(2), 1077–1091 (2021)CrossRef
4.
go back to reference N. Ahamad, A. Sikander, G. Singh, Substructure preservation based approach for discrete time system approximation. Microsyst. Technol. 25, 641–649 (2019)CrossRef N. Ahamad, A. Sikander, G. Singh, Substructure preservation based approach for discrete time system approximation. Microsyst. Technol. 25, 641–649 (2019)CrossRef
5.
go back to reference N. Ahamad, A. Sikander, G. Singh, Order diminution and its application in controller design using salp swarm optimization technique. Int. J. Syst. Assur. Eng. Manag. 13(2), 933–943 (2022)CrossRef N. Ahamad, A. Sikander, G. Singh, Order diminution and its application in controller design using salp swarm optimization technique. Int. J. Syst. Assur. Eng. Manag. 13(2), 933–943 (2022)CrossRef
6.
go back to reference N. Ahamad, G. Singh, S. Khan, A. Sikander, Design and performance analysis of optimal reduced order H-infinity controller: L1 norm based genetic algorithm technique. In International Conference on Power and Embedded Drive Control (2017), pp. 8–13 N. Ahamad, G. Singh, S. Khan, A. Sikander, Design and performance analysis of optimal reduced order H-infinity controller: L1 norm based genetic algorithm technique. In International Conference on Power and Embedded Drive Control (2017), pp. 8–13
8.
go back to reference N. Ahmed, G. Singh, M. Samir, H. Ahmad, Performance analysis of reduced order aircraft bank angle control system. In Conference on Advances in Communication and Control Systems (CAC2S 2013) (2013), pp. 518–520 N. Ahmed, G. Singh, M. Samir, H. Ahmad, Performance analysis of reduced order aircraft bank angle control system. In Conference on Advances in Communication and Control Systems (CAC2S 2013) (2013), pp. 518–520
9.
go back to reference P. Benner, A. Schneider, Reduced representation of power grid models. Syst. Reduct. Nanoscale IC Des. 87–134 (2017) P. Benner, A. Schneider, Reduced representation of power grid models. Syst. Reduct. Nanoscale IC Des. 87–134 (2017)
10.
go back to reference A. Charest, D. Saraswat, M. Nakhla, R. Achar, N. Soveiko, Compact macromodeling of high-speed circuits via delayed rational functions. IEEE Microw. Wirel. Compon. Lett. 17(12), 828–830 (2007)CrossRef A. Charest, D. Saraswat, M. Nakhla, R. Achar, N. Soveiko, Compact macromodeling of high-speed circuits via delayed rational functions. IEEE Microw. Wirel. Compon. Lett. 17(12), 828–830 (2007)CrossRef
11.
go back to reference Y. Chen, V. Balakrishnan, C.K. Koh, K. Roy, Model reduction in the time-domain using Laguerre polynomials and Krylov methods. In Proceedings of the Conference on Design, Automation and Test, Europe (2002), pp. 931–935 Y. Chen, V. Balakrishnan, C.K. Koh, K. Roy, Model reduction in the time-domain using Laguerre polynomials and Krylov methods. In Proceedings of the Conference on Design, Automation and Test, Europe (2002), pp. 931–935
12.
go back to reference X. Chen, Y. Wang, H. Yang, Parallel Sparse Direct Solver for Integrated Circuit Simulation (Springer International Publishing, 2017), pp. 3–4 X. Chen, Y. Wang, H. Yang, Parallel Sparse Direct Solver for Integrated Circuit Simulation (Springer International Publishing, 2017), pp. 3–4
13.
go back to reference A. Chinea, P. Triverio, S. Grivet-Talocia, Delay-based macromodeling of long interconnects from frequency-domain terminal responses. IEEE Trans. Adv. Packag. 33(1), 246–256 (2010)CrossRef A. Chinea, P. Triverio, S. Grivet-Talocia, Delay-based macromodeling of long interconnects from frequency-domain terminal responses. IEEE Trans. Adv. Packag. 33(1), 246–256 (2010)CrossRef
14.
go back to reference J. Cullum, A. Ruehli, T. Zhang, A method for reduced-order modeling and simulation of large interconnect circuits and its application to PEEC models with retardation. IEEE Trans. Circuits Syst. II Analog Digit. Signal Process. 47(4), 261–273 (2000)CrossRef J. Cullum, A. Ruehli, T. Zhang, A method for reduced-order modeling and simulation of large interconnect circuits and its application to PEEC models with retardation. IEEE Trans. Circuits Syst. II Analog Digit. Signal Process. 47(4), 261–273 (2000)CrossRef
15.
go back to reference J. Elias, T. Damm, W. Michiels, Model reduction of time-delay systems using position balancing and delay Lyapunov equations. Math. Control Signals Syst. 25(2), 147–166 (2013)MathSciNetCrossRef J. Elias, T. Damm, W. Michiels, Model reduction of time-delay systems using position balancing and delay Lyapunov equations. Math. Control Signals Syst. 25(2), 147–166 (2013)MathSciNetCrossRef
16.
go back to reference P. Feldmann, R. Freund, Efficient linear circuit analysis by Padé approximation via the Lanczos process. IEEE Trans. Comput Aided Des. Integr. Circuits Syst. 14, 639–649 (1995)CrossRef P. Feldmann, R. Freund, Efficient linear circuit analysis by Padé approximation via the Lanczos process. IEEE Trans. Comput Aided Des. Integr. Circuits Syst. 14, 639–649 (1995)CrossRef
17.
go back to reference L. Feng, L. Lombardi, P. Benner, D. Romano, G. Antonini, Model order reduction for delayed PEEC models with guaranteed accuracy and observed stability. IEEE Trans. Circuits Syst. I Regul. Pap. 69(10), 4177–4190 (2022)CrossRef L. Feng, L. Lombardi, P. Benner, D. Romano, G. Antonini, Model order reduction for delayed PEEC models with guaranteed accuracy and observed stability. IEEE Trans. Circuits Syst. I Regul. Pap. 69(10), 4177–4190 (2022)CrossRef
18.
go back to reference R.W. Freund, SPRIM: structure-preserving reduced-order interconnect macromodeling. In Proceedings of the IEEE/ACM International Conference on Computer Aided Design, CA, USA (2004), pp. 80–87 R.W. Freund, SPRIM: structure-preserving reduced-order interconnect macromodeling. In Proceedings of the IEEE/ACM International Conference on Computer Aided Design, CA, USA (2004), pp. 80–87
19.
go back to reference P.K. Gunupudi, M. Nakhia, R. Achar, Simulation of high-speed distributed interconnects using Krylov-space techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(7), 799–808 (2000)CrossRef P.K. Gunupudi, M. Nakhia, R. Achar, Simulation of high-speed distributed interconnects using Krylov-space techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(7), 799–808 (2000)CrossRef
20.
go back to reference Y. Huang, Y.L. Jiang, K.L. Xu, Model order reduction of RLC circuit system modeled by Port-Hamiltonian structure. IEEE Trans. Circuits Syst. II Express Briefs 69(3), 1542–1546 (2022) Y. Huang, Y.L. Jiang, K.L. Xu, Model order reduction of RLC circuit system modeled by Port-Hamiltonian structure. IEEE Trans. Circuits Syst. II Express Briefs 69(3), 1542–1546 (2022)
21.
go back to reference S. Jain, Y.V. Hote, Order diminution of LTI systems using modified big bang big crunch algorithm and Pade approximation with fractional order controller design. Int. J. Control Autom. Syst. 19, 2105–2121 (2021)CrossRef S. Jain, Y.V. Hote, Order diminution of LTI systems using modified big bang big crunch algorithm and Pade approximation with fractional order controller design. Int. J. Control Autom. Syst. 19, 2105–2121 (2021)CrossRef
22.
go back to reference Y.L. Jiang, H.B. Chen, Time domain model order reduction of general orthogonal polynomials for linear input–output systems. IEEE Trans. Automat. Contr. 57(2), 330–343 (2012)MathSciNetCrossRef Y.L. Jiang, H.B. Chen, Time domain model order reduction of general orthogonal polynomials for linear input–output systems. IEEE Trans. Automat. Contr. 57(2), 330–343 (2012)MathSciNetCrossRef
23.
go back to reference Y.L. Jiang, K.L. Xu, Frequency-limited reduced models for linear and bilinear systems on the Riemannian manifold. IEEE Trans. Automat. Contr. 66(9), 3938–3951 (2021)MathSciNetCrossRef Y.L. Jiang, K.L. Xu, Frequency-limited reduced models for linear and bilinear systems on the Riemannian manifold. IEEE Trans. Automat. Contr. 66(9), 3938–3951 (2021)MathSciNetCrossRef
24.
go back to reference Y.L. Jiang, J.M. Yang, Asymptotic waveform evaluation with higher order poles. IEEE Trans. Circuits Syst. I Regul. Pap. 68(4), 1681–1692 (2021)MathSciNetCrossRef Y.L. Jiang, J.M. Yang, Asymptotic waveform evaluation with higher order poles. IEEE Trans. Circuits Syst. I Regul. Pap. 68(4), 1681–1692 (2021)MathSciNetCrossRef
25.
go back to reference L. Knockaert, D. De Zutter, Laguerre-SVD reduced-order modeling. IEEE Trans. Microw. Theory Tech. 48(9), 1469–1475 (2000)CrossRef L. Knockaert, D. De Zutter, Laguerre-SVD reduced-order modeling. IEEE Trans. Microw. Theory Tech. 48(9), 1469–1475 (2000)CrossRef
26.
go back to reference J. Lam, Model reduction of delay systems using Pad approximants. Int. J. Control 57(2), 377–391 (2012)CrossRef J. Lam, Model reduction of delay systems using Pad approximants. Int. J. Control 57(2), 377–391 (2012)CrossRef
27.
go back to reference L. Lombardi, Y. Tao, B. Nouri, F. Ferranti, G. Antonini, M.S. Nakhla, Parameterized model order reduction of delayed PEEC circuits. IEEE Trans. Electromagn. Compat. 62(3), 859–869 (2020)CrossRef L. Lombardi, Y. Tao, B. Nouri, F. Ferranti, G. Antonini, M.S. Nakhla, Parameterized model order reduction of delayed PEEC circuits. IEEE Trans. Electromagn. Compat. 62(3), 859–869 (2020)CrossRef
28.
go back to reference A. Odabasioglu, M. Celik, L.T. Pileggi, PRIMA: Passive reduced-order interconnect macromodeling algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(8), 645–654 (1998)CrossRef A. Odabasioglu, M. Celik, L.T. Pileggi, PRIMA: Passive reduced-order interconnect macromodeling algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(8), 645–654 (1998)CrossRef
29.
go back to reference J.R. Phillips, L.M. Silveira, Poor man’s TBR: a simple model reduction scheme. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(1), 43–55 (2005)CrossRef J.R. Phillips, L.M. Silveira, Poor man’s TBR: a simple model reduction scheme. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(1), 43–55 (2005)CrossRef
30.
go back to reference L.T. Pillage, R.A. Rohrer, Asymptotic waveform evaluation for timing analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9, 352–366 (1990)CrossRef L.T. Pillage, R.A. Rohrer, Asymptotic waveform evaluation for timing analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9, 352–366 (1990)CrossRef
31.
go back to reference Z.Y. Qiu, Y.L. Jiang, \(\varepsilon \)—Embedding model reduction method for time-delay differential algebra systems. Circuits Syst. Signal Process. 39(11), 5390–5405 (2020)CrossRef Z.Y. Qiu, Y.L. Jiang, \(\varepsilon \)—Embedding model reduction method for time-delay differential algebra systems. Circuits Syst. Signal Process. 39(11), 5390–5405 (2020)CrossRef
32.
go back to reference T. Reis, T. Stykel, PABTEC: passivity-preserving balanced truncation for electrical circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(9), 1354–367 (2010)CrossRef T. Reis, T. Stykel, PABTEC: passivity-preserving balanced truncation for electrical circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(9), 1354–367 (2010)CrossRef
33.
go back to reference E.R. Samuel, L. Knockaert, T. Dhaene, Model order reduction of time-delay systems using a Laguerre expansion technique. IEEE Trans. Circuits Syst. I Regul. Pap. 61(6), 1815–1823 (2014)CrossRef E.R. Samuel, L. Knockaert, T. Dhaene, Model order reduction of time-delay systems using a Laguerre expansion technique. IEEE Trans. Circuits Syst. I Regul. Pap. 61(6), 1815–1823 (2014)CrossRef
34.
go back to reference A. Sikander, R. Prasad, Soft computing approach for model order reduction of linear time invariant systems. Circuits Syst. Signal Process. 34, 3471–3487 (2015)CrossRef A. Sikander, R. Prasad, Soft computing approach for model order reduction of linear time invariant systems. Circuits Syst. Signal Process. 34, 3471–3487 (2015)CrossRef
35.
go back to reference H. P. Singh, G.S. Virdi, RLC modeled interconnect delay analysis for high-speed on-chip VLSI interconnects. In 2017 International Conference on Energy, Communication, Data Analytics and Soft Computing (2017), pp. 2199–2203 H. P. Singh, G.S. Virdi, RLC modeled interconnect delay analysis for high-speed on-chip VLSI interconnects. In 2017 International Conference on Energy, Communication, Data Analytics and Soft Computing (2017), pp. 2199–2203
36.
go back to reference T. Stykel, Balancing-related model reduction of circuit equations using topological structure. In: Model Reduction For Circuit Simulation (2011), pp. 53–83 T. Stykel, Balancing-related model reduction of circuit equations using topological structure. In: Model Reduction For Circuit Simulation (2011), pp. 53–83
37.
go back to reference W. Tseng, C. Chen, E. Gad, M. Nakhla, R. Achar, Passive order reduction for RLC circuits with delay elements. IEEE Trans. Adv. Packag. 30(4), 830–840 (2007)CrossRef W. Tseng, C. Chen, E. Gad, M. Nakhla, R. Achar, Passive order reduction for RLC circuits with delay elements. IEEE Trans. Adv. Packag. 30(4), 830–840 (2007)CrossRef
38.
go back to reference X.L. Wang, Y.L. Jiang, An efficient hybrid reduction method for time-delay systems using Hermite expansions. Int. J. Control 92(5), 1033–1043 (2019)MathSciNetCrossRef X.L. Wang, Y.L. Jiang, An efficient hybrid reduction method for time-delay systems using Hermite expansions. Int. J. Control 92(5), 1033–1043 (2019)MathSciNetCrossRef
39.
go back to reference S. Wil, The need for novel model order reduction techniques in the electronics industry. In: Model Reduction for Circuit Simulation (Springer Netherlands, Dordrecht, 2011), pp. 3–23 S. Wil, The need for novel model order reduction techniques in the electronics industry. In: Model Reduction for Circuit Simulation (Springer Netherlands, Dordrecht, 2011), pp. 3–23
40.
go back to reference H. Yang, Y. Zhang, X. Huang, S. Hong, Positivity and exponential stability of coupled homogeneous time-delay differential-difference equations of degree one. Circuits Syst. Signal Process. 41(2), 762–788 (2022)CrossRef H. Yang, Y. Zhang, X. Huang, S. Hong, Positivity and exponential stability of coupled homogeneous time-delay differential-difference equations of degree one. Circuits Syst. Signal Process. 41(2), 762–788 (2022)CrossRef
Metadata
Title
Hermite Expansion Technique for Model Reduction of Circuit Systems with Delay Components
Authors
Zhi-Yong Qiu
Zhen-Hua Guo
Yao-Lin Jiang
Ya-Qian Zhao
Ren-Gang Li
Publication date
16-06-2024
Publisher
Springer US
Published in
Circuits, Systems, and Signal Processing / Issue 9/2024
Print ISSN: 0278-081X
Electronic ISSN: 1531-5878
DOI
https://doi.org/10.1007/s00034-024-02750-x