3. Heterogeneous Approximate Multipliers: Architectures and Design Methodologies

Multipliers are an integral block of a wide range of error-resilient applications like audio, image, and video processing, and machine learning. However, these multiplier architectures are computationally complex, and hence consume more power and occupy more area with long carry-adder trees when implementing multipliers with high bit-width. Approximate computing is an emerging design paradigm and is currently exploited to alleviate such area and power overheads, with slight/affordable degradation in the output quality of error-resilient application. An approximate multiplier architecture could either be approximated at the partial-product generation, accumulation, or summation stages. In this chapter, we focus on the different design aspects of energy-efficient approximate multipliers for both ASICs- and FPGAs-based systems.