High Efficiency Power Amplifier Design for 28 GHz 5G Transmitters

Table of Contents

1. Frontmatter

2. Chapter 1. Introduction

   Nourhan Elsayed, Hani Saleh, Baker Mohammad, Mohammed Ismail, Mihai Sanduleanu

   Abstract

   This chapter introduces the motivation behind this book. It provides an introduction to the reasons driving the move toward the 5G communication scheme and the challenges it presents for research toward new design methods for transceiver architectures. A general book organization will also be provided at the end of the chapter.

3. Chapter 2. Power Amplifier Fundamentals

   Nourhan Elsayed, Hani Saleh, Baker Mohammad, Mohammed Ismail, Mihai Sanduleanu

   Abstract

   This chapter provides basic definitions of power amplifier fundamentals starting with performance measures for efficiency and linearity. The characterization of different power amplifier classes and challenges is also discussed followed by different techniques in the literature used to overcome them.

4. Chapter 3. Doherty Power Amplifier

   Nourhan Elsayed, Hani Saleh, Baker Mohammad, Mohammed Ismail, Mihai Sanduleanu

   Abstract

   This chapter discusses the design of a 2-way Doherty PA at 28 GHz with high efficiency at peak and back-off. It demonstrates the capability of the 22nm FDSOI 5G circuit and systems that utilize the strengths of the 22 nm FDSOI technology to provide maximum performance. Section 3.1 elaborates on the design steps of the Doherty power amplifier. Simulation and measurement results along with comparison with the existing state-of-the-art DPAs are discussed in Sect. 3.2. Finally, Sect. 3.3 summarizes the chapter.

5. Chapter 4. Delayed Switched Cascode Class-E Amplifier

   Nourhan Elsayed, Hani Saleh, Baker Mohammad, Mohammed Ismail, Mihai Sanduleanu

   Abstract

   This chapter discusses the application of a novel switched mode Class-E PA implemented in 22 nm FDSOI technology. The Class-E PA relies on switching not only the input device, but also the cascode device with a 50% duty cycle signal in order to minimize the overlap between the output voltage and the current (pulse injection). Not only will the cascode device be switched, but an added delay element between the input and output transistors is employed. This modification of the delayed phase will result in more control over the power consumption and hence the DE and PAE. This chapter is organized as follows: Sect. 4.1 discusses the switched cascode Class-E PA design and architecture. Followed by Sect. 4.2 that presents the implementation and measurement results. Section 4.3 provides a summary.

6. Chapter 5. Delayed Switched Cascode Doherty Class-E PA

   Nourhan Elsayed, Hani Saleh, Baker Mohammad, Mohammed Ismail, Mihai Sanduleanu

   Abstract

   This chapter presents the first completely on-chip Doherty based Class-E PA in 22nm FDSOI. The PAs include a cascode topology for improved efficiency and a larger output power. To further improve the total PAE, the switching signal is applied to the input transistor of the Class-E PA as well as to the cascode transistor with a delay element that utilizes a tunable transmission line. The Doherty PA is preceded by an active balun that produces two 180^∘ out-of-phase signals followed by a variable gain amplifier (VGA). To the best of our knowledge this is the first Doherty design with switched cascode Class-E amplifier. Section 5.1 discusses the switched mode Class-E DPA Design and architecture. Section 5.2 presents the implementation and measurement results. Finally, Sect. 5.3 concludes the chapter.

7. Chapter 6. A 28 GHz Inverse Class-D Power Amplifier

   Nourhan Elsayed, Hani Saleh, Baker Mohammad, Mohammed Ismail, Mihai Sanduleanu

   Abstract

   This chapter presents design, simulation, and measurements of a current mode/inverse Class-D (CMCD) PA at 28 GHz utilizing Global Foundries’ 22 nm FDSOI technology. In order to overcome the breakdown voltage of the devices, increase efficiency, and deliver more output power, the implemented PA utilizes the cascode (stacking) topology. Pulse injection from the input transistor into the stacked transistor in order to minimize the output capacitance and achieve higher efficiency. This chapter is organized as follows: Sect. 6.1 discusses the principle of operation of the classical CMCD, and Sect. 6.2 presents the design methodology of the proposed CMCD and introduces the concept of utilizing a cascode topology along with pulse injection. Section 6.3 discusses measurement results and comparison to the state-of-the-art CMCD PAs and Sect. 6.4 concludes the chapter.

8. Chapter 7. Phased-Array Transmitter

   Nourhan Elsayed, Hani Saleh, Baker Mohammad, Mohammed Ismail, Mihai Sanduleanu

   Abstract

   This chapter presents the design and simulation of a 4-phased-array transmitter utilizing the Class-E based Doherty PA in 22nm FDSOI. The transmitter design includes the signal from the baseband to the front-end PA module. It utilizes a novel active 1:4 power divider preceding the PA and tunable transmission lines as delay elements. Section 7.1 discusses the conventional direct conversion transmitter architecture, and Sect. 7.2 discusses the proposed phased-array transmitter design. Section 7.3 goes into the details of the blocks used for LO quadrature generation including the polyphase filter, phase rotator, and the mixer. Sections 7.4 and 7.5 present the design of the tunable low pass filter and the low frequency VGA, respectively. Section 7.6 elaborates on the design of the power divider, while Sect. 7.7 covers the simulation results of the 4-phased-array transmitter.

9. Backmatter