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Low-Power, High-Speed and High-Effective Resolution Pipeline Analog-to-Digital Converters in Deep Nanoscale CMOS Read chapter Read first chapter

2015 | OriginalPaper | Chapter

High-Performance DACs: Unifying 16-Bit Dynamic Range with GS/s Data-Rates

Authors : Joost Briaire, Pieter van Beek, Govert Geelen, Hans Van de Vel, Harrie Gunnink, Yongjie Jin, Mustafa Kaba, Kerong Luo, Corné Bastiaansen, Bang Pham, William Relyveld, Peter Zijlstra, Edward Paulus

Published in: High-Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing

Publisher: Springer International Publishing

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Abstract

Analysis of recent publications reveals that high performance DAC design can be sub-divided into two types of design approaches. In essence these approaches differ as far as the control of mismatch related effects is concerned. On the one hand one can design such that these effects are intrinsically sufficiently under control but then additional advanced design techniques are required to limit the side-effects of this intrinsic approach. On the other hand one can also rely on mismatch calibration to simplify the design itself. For this approach we will also focus on a more recent specific calibration concept for high performance DACs to unify 16-bit dynamic range with GS/s data-rates. Both approaches have their strengths and weaknesses and depending on the application either one could be more favorable.

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Metadata
Title
High-Performance DACs: Unifying 16-Bit Dynamic Range with GS/s Data-Rates
Authors
Joost Briaire
Pieter van Beek
Govert Geelen
Hans Van de Vel
Harrie Gunnink
Yongjie Jin
Mustafa Kaba
Kerong Luo
Corné Bastiaansen
Bang Pham
William Relyveld
Peter Zijlstra
Edward Paulus
Copyright Year
2015
Book
High-Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing

Print ISBN: 978-3-319-07937-0

Electronic ISBN: 978-3-319-07938-7

Copyright Year: 2015

DOI
https://doi.org/10.1007/978-3-319-07938-7_6