Skip to main content
Top

2016 | OriginalPaper | Chapter

6. High-Radix Arithmetic-Logic Unit (ALU) Based on Memristors

Authors : Ioannis Vourkas, Georgios Ch. Sirakoulis

Published in: Memristor-Based Nanoelectronic Computing Circuits and Architectures

Publisher: Springer International Publishing

Activate our intelligent search to find suitable subject content or patents.

search-config
loading …

Abstract

This chapter presents a novel method for implementing crossbar-based multi-level memories, where each cross-point cell stores multiple bits. Furthermore, a conceptual solution for novel CMOS-compatible, memristive, high-radix arithmetic logic units (ALUs) is proposed, for future computing systems. More specifically, a hybrid ALU circuit nano-architecture is described, where: (a) CMOS peripheral circuits are used for binary arithmetic operations; (b) a memristive reconfigurable crossbar-based memory block is used to: (i) allow parallel read/write of data; (ii) facilitate the implementation of efficient arithmetic algorithms (e.g. fast partial product creation for multiplication); and (iii) store information in a compact, high-radix form. Instead of single memristors, the crossbar nodes comprise a type of multi-state composite memristive switches, described in Chap. 3, which permit multi-bit storage in a more robust manner. Radix-4 representation is used because: (i) it balances the offered advantages with the peripheral binary conversion circuitry overhead; and (ii) it provides a good density/reliability trade-off. The fine operation and accuracy of the proposed system architecture is demonstrated through SPICE-level simulations.

Dont have a licence yet? Then find out more about our products and how to get one now:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

  • über 102.000 Bücher
  • über 537 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Maschinenbau + Werkstoffe
  • Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 390 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Maschinenbau + Werkstoffe




 

Jetzt Wissensvorsprung sichern!

Literature
1.
go back to reference R.P. Brent, P. Zimmermann, Modern Computer Arithmetic (Cambridge University Press, Cambridge, 2010)CrossRefMATH R.P. Brent, P. Zimmermann, Modern Computer Arithmetic (Cambridge University Press, Cambridge, 2010)CrossRefMATH
3.
go back to reference S. Hamdioui, H. Aziza, G.C. Sirakoulis, “Memristor Based Memories: Technology, Design and Test, in 9th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), Santorini island, Greece (2014) S. Hamdioui, H. Aziza, G.C. Sirakoulis, “Memristor Based Memories: Technology, Design and Test, in 9th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), Santorini island, Greece (2014)
4.
go back to reference Y. Pershin, M. Di Ventra, Practical approach to programmable analog circuits with memristors. IEEE Trans. Circ. Syst. I, Reg. Papers 57(8), 1857–1864 (2010)MathSciNetCrossRef Y. Pershin, M. Di Ventra, Practical approach to programmable analog circuits with memristors. IEEE Trans. Circ. Syst. I, Reg. Papers 57(8), 1857–1864 (2010)MathSciNetCrossRef
5.
go back to reference E. Lehtonen, M. Laiho, Stateful implication logic with memristors, in IEEE/ACM International Symposium on. Nanoscale Architectures (NANOARCH), San Francisco, CA (2009) E. Lehtonen, M. Laiho, Stateful implication logic with memristors, in IEEE/ACM International Symposium on. Nanoscale Architectures (NANOARCH), San Francisco, CA (2009)
6.
go back to reference S. Kvatinsky, G. Satat, N. Wald, E.G. Friedman, A. Kolodny, U.C. Weiser, Memristor-based material implication (IMPLY) logic: design principles and methodologies, IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 22(10), 2054–2066 (2014) S. Kvatinsky, G. Satat, N. Wald, E.G. Friedman, A. Kolodny, U.C. Weiser, Memristor-based material implication (IMPLY) logic: design principles and methodologies, IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 22(10), 2054–2066 (2014)
7.
go back to reference S. Paul, S. Bhunia, A scalable memory-based reconfigurable computing framework for nanoscale crossbar. IEEE Trans. Nanotechnol. 11(3), 451–462 (2012)CrossRef S. Paul, S. Bhunia, A scalable memory-based reconfigurable computing framework for nanoscale crossbar. IEEE Trans. Nanotechnol. 11(3), 451–462 (2012)CrossRef
8.
go back to reference G.S. Rose, J. Rajendran, H. Manem, R. Karri, R.E. Pino, Leveraging memristive systems in the construction of digital logic circuits. IEEE Proc. 100(6), 2033–2049 (2012)CrossRef G.S. Rose, J. Rajendran, H. Manem, R. Karri, R.E. Pino, Leveraging memristive systems in the construction of digital logic circuits. IEEE Proc. 100(6), 2033–2049 (2012)CrossRef
9.
go back to reference G. Papandroulidakis, I. Vourkas, N. Vasileiadis, G.C. Sirakoulis, Boolean logic operations and computing circuits based on memristors. IEEE Trans. Circuits Syst. II Expr. Briefs 61(12), 972–976 (2014)CrossRef G. Papandroulidakis, I. Vourkas, N. Vasileiadis, G.C. Sirakoulis, Boolean logic operations and computing circuits based on memristors. IEEE Trans. Circuits Syst. II Expr. Briefs 61(12), 972–976 (2014)CrossRef
10.
go back to reference R. Patel, E.G. Friedman, Arithmetic encoding for memristive multi-bit storage, in 20th IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC), Santa Cruz, CA (2012) R. Patel, E.G. Friedman, Arithmetic encoding for memristive multi-bit storage, in 20th IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC), Santa Cruz, CA (2012)
12.
13.
go back to reference C.E. Merkel, N. Nagpal, S. Mandalapu, D. Kudithipudi, Reconfigurable N-level memristor memory design, in International Joint Conference on Neural Networks (IJCNN), San Jose, CA (2011) C.E. Merkel, N. Nagpal, S. Mandalapu, D. Kudithipudi, Reconfigurable N-level memristor memory design, in International Joint Conference on Neural Networks (IJCNN), San Jose, CA (2011)
14.
go back to reference K. Hyongsuk, M.P. Sah, C. Yang, L.O. Chua, Memristor-based multilevel memory, in 12th International Workshop on Cellular Nanoscale Networks and Their Applications (CNNA), Berkeley, CA (2010) K. Hyongsuk, M.P. Sah, C. Yang, L.O. Chua, Memristor-based multilevel memory, in 12th International Workshop on Cellular Nanoscale Networks and Their Applications (CNNA), Berkeley, CA (2010)
15.
go back to reference H. Manem, J. Rajendran, G.S. Rose, Design considerations for multilevel CMOS/Nano memristive memory. ACM J. Emerg. Technol. Comput. Syst. 8(16), 1–22 (2012)CrossRef H. Manem, J. Rajendran, G.S. Rose, Design considerations for multilevel CMOS/Nano memristive memory. ACM J. Emerg. Technol. Comput. Syst. 8(16), 1–22 (2012)CrossRef
16.
go back to reference A. Emara, M. Ghoneima, M. El-Dessouky, Differential 1T2M memristor memory cell for single/multi-bit RRAM modules, in 6th Computer Science and Electronic Engineering Conference (CEEC), Colchester (2014) A. Emara, M. Ghoneima, M. El-Dessouky, Differential 1T2M memristor memory cell for single/multi-bit RRAM modules, in 6th Computer Science and Electronic Engineering Conference (CEEC), Colchester (2014)
17.
go back to reference D. Fey, Using the multi-bit feature of memristors for register files in signed-digit arithmetic units. Semicond. Sci. Technol. 29, 104008 (2014)CrossRef D. Fey, Using the multi-bit feature of memristors for register files in signed-digit arithmetic units. Semicond. Sci. Technol. 29, 104008 (2014)CrossRef
18.
go back to reference Y.V. Pershin, M. Di Ventra, Memory effects in complex materials and nanoscale systems. Adv. Phys. 60(2), 145–227 (2011)CrossRef Y.V. Pershin, M. Di Ventra, Memory effects in complex materials and nanoscale systems. Adv. Phys. 60(2), 145–227 (2011)CrossRef
19.
go back to reference E. Linn, R. Rosezin, S. Tappertzhofen, U. Bottger, R. Waser, Beyond von Neumann-logic operations in passive crossbar arrays alongside memory operations, Nanotechnology 23, 305205 (2012) E. Linn, R. Rosezin, S. Tappertzhofen, U. Bottger, R. Waser, Beyond von Neumann-logic operations in passive crossbar arrays alongside memory operations, Nanotechnology 23, 305205 (2012)
20.
go back to reference M. Di Ventra, Y.V. Pershin, The parallel approach. Nat. Phys. 9, 200–202 (2013)CrossRef M. Di Ventra, Y.V. Pershin, The parallel approach. Nat. Phys. 9, 200–202 (2013)CrossRef
21.
go back to reference K.H. Kim, S. Gaba, D. Wheeler, J.M. Cruz-Albrecht, T. Hussain, N. Srinivasa, W. Lu, A functional hybrid memristor crossbar-array/CMOS system for data storage and neuromorphic applications. Nano Lett. 12(1), 389–395 (2012)CrossRef K.H. Kim, S. Gaba, D. Wheeler, J.M. Cruz-Albrecht, T. Hussain, N. Srinivasa, W. Lu, A functional hybrid memristor crossbar-array/CMOS system for data storage and neuromorphic applications. Nano Lett. 12(1), 389–395 (2012)CrossRef
22.
go back to reference H. Kim, M.P. Sah, C. Yang, T. Roska, L.O. Chua, Neural synaptic weighting with a pulse-based memristor circuit. IEEE Trans. Circ. Syst. I Reg. Papers 59(1), 148–158 (2012)MathSciNetCrossRef H. Kim, M.P. Sah, C. Yang, T. Roska, L.O. Chua, Neural synaptic weighting with a pulse-based memristor circuit. IEEE Trans. Circ. Syst. I Reg. Papers 59(1), 148–158 (2012)MathSciNetCrossRef
23.
go back to reference C. Yakopcic, R. Hasan, T.M. Taha, M. McLean, D. Palmer, Memristor-based neuron circuit and method for applying learning algorithm in SPICE?, IET Electron. Lett. 50(7), 492–494 (2014) C. Yakopcic, R. Hasan, T.M. Taha, M. McLean, D. Palmer, Memristor-based neuron circuit and method for applying learning algorithm in SPICE?, IET Electron. Lett. 50(7), 492–494 (2014)
24.
go back to reference H. Manem, G.S. Rose, X. He, W. Wang, Design considerations for variation tolerant multilevel CMOS/nano memristor memory, in 20th Great Lakes Symposium on VLSI (GLSVLSI), Providence, Rhode Island (2010) H. Manem, G.S. Rose, X. He, W. Wang, Design considerations for variation tolerant multilevel CMOS/nano memristor memory, in 20th Great Lakes Symposium on VLSI (GLSVLSI), Providence, Rhode Island (2010)
25.
go back to reference P. Junsangsri, F. Lombardi, A memristor-based TCAM (ternary content addressable memory) cell: design and evaluation, in Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI), Salt Lake City, Utah, USA (2012) P. Junsangsri, F. Lombardi, A memristor-based TCAM (ternary content addressable memory) cell: design and evaluation, in Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI), Salt Lake City, Utah, USA (2012)
26.
go back to reference I. Vourkas, G.C. Sirakoulis, On the analog computational characteristics of memristive networks, in 20th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Abu Dhabi (2013) I. Vourkas, G.C. Sirakoulis, On the analog computational characteristics of memristive networks, in 20th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Abu Dhabi (2013)
27.
go back to reference I. Vourkas, G.C. Sirakoulis, On the generalization of composite memristive network structures for computational analog/digital circuits and systems. Microelectron. J. 45(11), 1380–1391 (2014)CrossRef I. Vourkas, G.C. Sirakoulis, On the generalization of composite memristive network structures for computational analog/digital circuits and systems. Microelectron. J. 45(11), 1380–1391 (2014)CrossRef
28.
go back to reference I. Vourkas, A. Batsos, G.C. Sirakoulis, SPICE modeling of nonlinear memristive behavior, Int. J. Circ. Theor. Appl. 43(5), 553–565(2015) I. Vourkas, A. Batsos, G.C. Sirakoulis, SPICE modeling of nonlinear memristive behavior, Int. J. Circ. Theor. Appl. 43(5), 553–565(2015)
29.
go back to reference Y. Yilmaz, P. Mazumder, Threshold read method for multi-bit memristive crossbar memory, in Int. Symposium on Electronic System Design (ISED), Kochi, Kerala (2011) Y. Yilmaz, P. Mazumder, Threshold read method for multi-bit memristive crossbar memory, in Int. Symposium on Electronic System Design (ISED), Kochi, Kerala (2011)
30.
go back to reference K. Cho, S.J. Lee, K. Eshraghian, Memristor-CMOS logic and digital computational components. Microelectron. J. 46(3), 214–220 (2015)CrossRef K. Cho, S.J. Lee, K. Eshraghian, Memristor-CMOS logic and digital computational components. Microelectron. J. 46(3), 214–220 (2015)CrossRef
31.
go back to reference A.A. El-Slehdar, A.H. Fouad, A.G. Radwan, Memristor-based redundant binary adder, in International Conference on Engineering and Technology (ICET), Cairo (2014) A.A. El-Slehdar, A.H. Fouad, A.G. Radwan, Memristor-based redundant binary adder, in International Conference on Engineering and Technology (ICET), Cairo (2014)
32.
go back to reference A.A. El-Slehdar, A.H. Fouad, A.G. Radwan, Memristor-based balanced ternary adder, in 25th International Conference on Microelectronics (ICM), Beirut (2013) A.A. El-Slehdar, A.H. Fouad, A.G. Radwan, Memristor-based balanced ternary adder, in 25th International Conference on Microelectronics (ICM), Beirut (2013)
33.
go back to reference A.A. El-Slehdar, A.H. Fouad, A.G. Radwan, Memristor based N-bits redundant binary adder. Microelectron. J. 46(3), 207–213 (2015)CrossRef A.A. El-Slehdar, A.H. Fouad, A.G. Radwan, Memristor based N-bits redundant binary adder. Microelectron. J. 46(3), 207–213 (2015)CrossRef
34.
go back to reference M. Laiho, E. Lehtonen, Arithmetic operations within memristor-based analog memory, in 12th International Workshop on Cellular Nanoscale Networks and Their Applications (CNNA), Berkeley, CA (2010) M. Laiho, E. Lehtonen, Arithmetic operations within memristor-based analog memory, in 12th International Workshop on Cellular Nanoscale Networks and Their Applications (CNNA), Berkeley, CA (2010)
35.
go back to reference K. Bickerstaff, E.E. Swartzlander, Memristor-based arithmetic, in 44th Asilomar Conference on Signals, Systems and Computers (ASILOMAR), Pacific Grove, CA (2010) K. Bickerstaff, E.E. Swartzlander, Memristor-based arithmetic, in 44th Asilomar Conference on Signals, Systems and Computers (ASILOMAR), Pacific Grove, CA (2010)
36.
go back to reference F. Merrikh-Bayat, S. Bagheri Shouraki, Memristor-based circuits for performing basic arithmetic operations, in Procedia Computer Science—Proceedings of 2010 World Conference on Information Technology (WCIT), vol. 3 (2011), pp. 128–132 F. Merrikh-Bayat, S. Bagheri Shouraki, Memristor-based circuits for performing basic arithmetic operations, in Procedia Computer Science—Proceedings of 2010 World Conference on Information Technology (WCIT), vol. 3 (2011), pp. 128–132
37.
go back to reference A.H. Shaltoot, A.H. Madian, Memristor based carry lookahead adder architectures, in 55th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Boise, ID (2012) A.H. Shaltoot, A.H. Madian, Memristor based carry lookahead adder architectures, in 55th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Boise, ID (2012)
38.
go back to reference Y. Yang, J. Mathew, D.K. Pradhan, M. Ottavi, S. Pontarelli, Complementary resistive switch based stateful logic operations using material implication, in Design, Automation and Test in Europe Conference and Exhibition (DATE), Dresden (2014) Y. Yang, J. Mathew, D.K. Pradhan, M. Ottavi, S. Pontarelli, Complementary resistive switch based stateful logic operations using material implication, in Design, Automation and Test in Europe Conference and Exhibition (DATE), Dresden (2014)
39.
go back to reference S.J. Lee, B.S. Park, S.W. Cho, K. Cho, K. Eshraghian, Memristor-CMOS reconfigurable multiplier architecture, in 14th International Workshop on Cellular Nanoscale Networks and their Applications (CNNA), Notre Dame, IN (2014) S.J. Lee, B.S. Park, S.W. Cho, K. Cho, K. Eshraghian, Memristor-CMOS reconfigurable multiplier architecture, in 14th International Workshop on Cellular Nanoscale Networks and their Applications (CNNA), Notre Dame, IN (2014)
Metadata
Title
High-Radix Arithmetic-Logic Unit (ALU) Based on Memristors
Authors
Ioannis Vourkas
Georgios Ch. Sirakoulis
Copyright Year
2016
DOI
https://doi.org/10.1007/978-3-319-22647-7_6