Top

Published in:

2025 | OriginalPaper | Chapter

High-Speed Area Efficient Approximate Kogge–Stone Adder

Authors : Sudhakar Reddy Dantla, Prudhvi Tummala, Sarada Musala, Satish Kanapala

Published in: Proceedings of Third International Conference on Computational Electronics for Wireless Communications

Publisher: Springer Nature Singapore

Activate our intelligent search to find suitable subject content or patents.

search-config

AI-assisted search

Off

Abstract

Approximate parallel prefix adders are a type of circuit that can perform addition operations on binary numbers with high speed, low area, and less power. These circuits are designed to provide approximate results, which means that they sacrifice accuracy for efficiency. This trade-off makes them ideal for use in applications where speed is more important than precision. In recent years, there has been a growing interest in the improvement of these circuits, as they have the potential to revolutionize the field of digital signal processing. Kogge–Stone (KS) adder is a kind of parallel prefix adder that has the strong point of quickest addition primarily based on design time. Approximation Kogge–Stone (AxKS) adder is a variant of basic Kogge–Stone Adder that introduces a level of approximation in its operation. In this paper, a new approximate KS Adder is proposed with high-speed performance and less area. The KS Adder and its AxKS Adder are compared for bits 8, 16, 32 using software tool Xilinx Vivado.

Dont have a licence yet? Then find out more about our products and how to get one now:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

über 102.000 Bücher
über 537 Zeitschriften

aus folgenden Fachgebieten:

Automobil + Motoren
Bauwesen + Immobilien
Business IT + Informatik
Elektrotechnik + Elektronik
Energie + Nachhaltigkeit
Finance + Banking
Management + Führung
Marketing + Vertrieb
Maschinenbau + Werkstoffe
Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

inform now

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

über 67.000 Bücher
über 390 Zeitschriften

aus folgenden Fachgebieten:

Automobil + Motoren
Bauwesen + Immobilien
Business IT + Informatik
Elektrotechnik + Elektronik
Energie + Nachhaltigkeit
Maschinenbau + Werkstoffe

Jetzt Wissensvorsprung sichern!

inform now

previous chapter Design and Analysis of Filtenna Array for C-Band Applications

next chapter Comparative Analysis of Neural Network Models for Error Probability Prediction in Vehicular Communication

Geetha BC, Lohitha DM, Navya, Pramod N (2018) Performance analaysis of parallel prefix adder datapath VLSI design. IEEE Xplore Compliant—Part Number: CFP18BAC-ART. ISBN 978-1-5386-1974-2, V

Azevedo da Rosa MM et al (2023) AxPPA: approximate parallel prefix adders. IEEE Trans Very Large Scale Integr (VLSI) Syst 31

Penchalaiah U, Vg SK (2018) Design of high-speed and energy-efficient parallel prefix kogge stone adder. In: IEEE ınternational conference on system, computation, automation and networking (ICSCA). IEEE, pp 1–7. https://doi.org/10.1109/ICSCAN.2018.8541143

Chowdhury SR, Banerjee A, Roy A, Saha H (2007) Design of high performance low power 16 bit arithmetic units using Kogge-Stone parallel prefix adder architectures. In: Proceedings of the SPIT-IEEE colloquium and ınternational conference, Mumbai, India, vol 2, pp 1–5

Varshney N, Arya G (2019) Design and execution of enhanced carry ıncrement adder using Han-Carlson and Kogge-Stone adder technique. In: IEEE conference on electronics communication and aerospace technology

Pashaeifar M, Kamal M, Afzali-Kusha A, Pedram M (2019) A theoretical framework for quality estimation and optimization of DSP applications using low-power approximate adders. IEEE Trans Circuits Syst I 66:327–340. https://doi.org/10.1109/TCSI.2018.2856757CrossRef

Stanley-Marbell P et al (2021) Exploiting errors for efficiency: a survey from circuits to applications. ACM Comput Surv 53:1–39. https://doi.org/10.1145/3394898CrossRef

Seidel HB et al (2021) Approximate pruned and truncatedHaar discrete wavelet transform VLSI hardware for energy-efficient signal processing. IEEE Trans Circuits Syst I Reg Pap 68:1814–1826

Pereira PTL et al (2022) Energy-quality scalable design space exploration of approximate FFT hardware architectures. IEEE Trans Circuits Syst I 69:4524–4534. https://doi.org/10.1109/TCSI.2022.3191180CrossRef

10.

Paim G et al (2019) Power-, area-, and compression-efficient eight-point approximate 2-D discrete tchebichef transform hardware design combining truncation pruning and efficient transposition buffers. IEEE Trans Circuits Syst I 66:680–693. https://doi.org/10.1109/TCSI.2018.2868513CrossRef

11.

Soares LB, Oliveira J, da Costa EAC, Bampi S (2020) An energy-efficient and approximate accelerator design for real-time Canny edge detection. Circuits Syst Signal Process 39:6098–6120. https://doi.org/10.1007/s00034-020-01448-0CrossRef

12.

Paim G, Amrouch H, Costa EACD, Bampi S, Henkel J (2022) Bridging the gap between voltage over-scaling and joint hardware accelerator-algorithm closed-loop. IEEE Trans Circ Syst Vitreoretinal 32(1):398–410

13.

Rani G, Kumar S (2012) Delay analysis of parallel-prefix adders. Int J Sci Res (IJSR). ISSN (Online) 2319-7064, Impact Factor 3.358

14.

Babulu K, Gowthami Y (2012) Implementation and performance evaluation of prefix adders using FPGAs. IOSR J. VLSI Signal Process. (IOSR-JVSP) 1:51–57. ISSN 2319-4200. ISBN No. 2319-4197

15.

Strollo AGM, Napoli E, De Caro D, Petra N, Di Meo G (2020) Comparison and extension of approximate 4–2compressors for low-power approximate multipliers. Circuits Syst I, Repapers (Trans IEEE) 67:3021–3034

16.

da Costa P et al (2022) Improved approximate multipliers for single-precision floating-point hardware design. In: Proceedings of the IEEE 13th Latin America symposium on circuits and system (LASCAS), Mar 2022, pp 1–4

17.

Talsania M, John E (2013) A comparative analysis of parallel prefix adders. In: Proceedings of the ınternational conference on computer design (cdes), P. 1. The Steering Committee of the World Congress in Computer Science, Computer Engineering and Applied Computing (WorldComp)

18.

Beaumont-Smith A, Lim C-C (2001) Parallel prefix adder design. In: Proceedings of the 15th IEEE symposium on computer arithmetic. ARITH-15. IEEE, pp 218–225. https://doi.org/10.1109/ARITH.2001.930122

19.

Kumar A, Kumar A, Nand D (2021) Design and study of dadda multiplier by using 4:2 compressors and parallel prefix adder for VLSI-circuit design. In: 2nd ınternational conference for emerging technology (INCET), Belgaum, India, 21–23 May 2021

20.

PrasannaKumar M, Sidhartan V, Gopalkrishnan K (2015) Comparative analysis of Brent Kung and Kogge Stone parallel prefix adders for their area, delay and power consumption. Engineering 5. ISSN 2249-555X

Title: High-Speed Area Efficient Approximate Kogge–Stone Adder
Authors: Sudhakar Reddy Dantla
Prudhvi Tummala
Sarada Musala
Satish Kanapala
Publisher: Springer Nature Singapore
Book: Proceedings of Third International Conference on Computational Electronics for Wireless Communications
Print ISBN: 978-981-9719-42-6

Electronic ISBN: 978-981-9719-43-3

Copyright Year: 2025
DOI: https://doi.org/10.1007/978-981-97-1943-3_18