2021 | OriginalPaper | Chapter Open Access

# 8. Impact of Negative Capacitance Field-Effect Transistor (NCFET) on Many-Core Systems

Authors: Hussam Amrouch, Martin Rapp, Sami Salamin, Jörg Henkel

Publisher: Springer International Publishing

## 8.1 Introduction

_{DD}− V

_{T}), where V

_{T}denotes the threshold voltage of transistor and V

_{DD}denotes the operating voltage. In order to maintain the same level of current, while V

_{DD}is scaled down, V

_{T}must also be reduced by almost the same amount. However, reducing V

_{T}comes with an exponential increase in the leakage current (OFF current) of transistor. This is primarily because that the sub-threshold swing of transistor is fundamentally limited to 60 mV/decade at room temperature akin to “Boltzmann tyranny” [ 21]. Such a fundamental limit inevitably restricts the minimum possible V

_{T}to be at least 300 mV. To ensure a reliable operation, different kinds of safety margins need to be added on top of the minimum voltage, which enforces the operating voltage to remain almost the same with every new technology generation. As above-mentioned, the inability to scale voltage has led to the discontinuation of Dennard’s scaling, which, in turn, had led to preventing the frequency of processors from increasing.

### 8.1.1 Negative Capacitance Field-Effect Transistor (NCFET)

## 8.2 Modeling NCFET at the System Level

### 8.2.1 Processor-Level Investigation

### 8.2.2 Simulation of NCFET-Based Many-Core

## 8.3 Performance, Power, and Cooling Trade-Offs with NCFET-based Many-Cores

^{∘}C. We study PARSEC [ 4] tasks with up to eight slave threads. Their characteristics range from highly memory-bound (e.g., canneal) to highly compute-bound (e.g., swaptions).

### 8.3.1 Impact of NCFET on Performance

### 8.3.2 Impact of NCFET on Cooling Requirements

_{th}. Varying this value corresponds to changing the air convection.

### 8.3.3 Impact of NCFET on Power Management Techniques

## 8.4 NCFET-Aware Voltage Scaling

_{opt}. Unawareness of NCFET and its trade-off could lead to not minimize the total power consumption. Therefore, in this section, a novel NCFET-aware voltage scaling technique is presented [ 17] to overcome the shortness that traditional DVS has in NCFET-based processors.

### 8.4.1 Importance of NCFET-Aware DVS

_{opt}could differ from \(V_{\min }\).

### 8.4.2 NCFET-Aware DVS Technique

_{opt}can be correctly selected. Therefore, determining V/f-pairs at runtime, like in traditional DVS techniques, is not possible here. Instead, the results from Sect. 8.2.1 have been used to build the power and performance analytical models at design time. Then, these models can be integrated with our new NCFET-aware DVS technique for runtime voltage selection.

#### 8.4.2.1 Design-Time Models

_{del}>0, b

_{del}<0, c

_{del}≥0 are constants fitting parameters obtained at design time. Peak leakage and peak dynamic power consumption results by operating at maximum frequency are

_{dyn}>0, b

_{dyn}>1, c

_{dyn}≥0, a

_{leak}>0, b

_{leak}<0 are constant fitting parameters obtained at design time. Both \({P}_{dyn}^{peak}(V,d_{\min }(V))\) and P

_{leak}( V ) are convex in V . By lowering the operating frequency of the CPU (higher delay), dynamic power decreases. However, since leakage power is independent from CPU activity, it is not affected.

_{dyn}+ b

_{del}>1.

#### 8.4.2.2 Runtime Models

_{dyn}( V, d) is affected by the running workload, which is reduced by a factor 0≤ r

_{dyn}≤1 from the peak dynamic power \(P_{dyn}^{peak}(V, d)\):

_{dyn}is not constant since it represents the current workload activity. Therefore, total power consumption P

_{total}( V

_{c}, d) at the current voltage V

_{c}, r

_{dyn}is

_{opt}that minimizes the total power can be obtained from the power and performance models:

_{total}( V, d) is composed of convex functions, our implemented algorithm exploits that P

_{total}( V, d) is convex in V . This guarantees that P

_{total}( V, d) has exactly one minimum w.r.t. V within the range \(\left [ V_{\min }(d),V_{\max }\right ]\). Algorithm 1 summarizes our implemented DVS technique and obtaining V

_{opt}.

_{opt}) at runtime [ 17]

### 8.4.3 Operating Voltage Selection

_{opt}) and NCFET-unaware DVS ( \(V_{\min }\)) has been explored in Fig. 8.7. NCFET-unaware DVS sets \(V_{\min }\) that is needed to sustain the required frequency and therefore workload characteristic is not considered. Contrarily, NCFET-aware DVS considers the workload characteristic as it depends on the ratio of leakage to total power measured at \(V_{\min }\). The explored design space in Fig. 8.7 shows two distinct regions: (1) For low leakage to total power ratio and for high frequencies, the same voltage is selected (similar action) by both techniques (i.e., \(V_{opt}{=}V_{\min }\)). (2) For high ratios of leakage to total power or low frequencies, NCFET-aware DVS selects a higher voltage ( \(V_{opt}{>}V_{\min }\)). Moreover, Fig. 8.7 reveals that: the higher the required frequency or the higher the leakage to total power ratio, the higher V

_{opt}is.

### 8.4.4 Evaluation

#### 8.4.4.1 Experimental Setup

_{dd}is set between 0.2 V and 0.7 V. The low operating voltages V

_{dd}in NCFET are lower than traditional FET due to the inherent voltage amplification in NCFET provided by the negative capacitance. For fair comparisons, simulators for both DVS cases were configured to have: the same frequencies, and architecture, in addition to running the same benchmarks. Hence, only voltage selection differs based on DVS decision.

#### 8.4.4.2 NCFET-Aware DVS Results and Analysis

_{dd}to the minimum voltage (0.28 V) which required to sustain this frequency. Thus, dynamic power is minimized but the leakage power is not. NCFET-aware DVS sets V

_{dd}to a higher value to guarantee a better trade-off. This will increase the dynamic power but strongly decreases leakage power resulting in a power saving. In phase-2, the master thread is idle and waits for the termination of the slave threads. Therefore, frequency is reduced to the minimum frequency (1.0 GHz). Traditional DVS reduces V

_{dd}to 0.2 V due to the low required frequency in which it increases the leakage power. NCFET-aware DVS, instead of reducing V

_{dd}, increases the voltage to 0.53 V, which decreases the leakage power. Thereby, the total power consumption in phase-2 is reduced by 67 % compared to the traditional DVS. In phase-3, after the slaves terminated, the master resumes operation and its frequency is boosted again to 1.7 GHz. It is worth to mention that the performance obtained with both DVS techniques is the same. This is because they do not affect the frequency, but only set the V

_{dd}under performance constraint.