Impact of Sidewall Spacer Layers on the Analog/RF Performance of Nanoscale Double-Gate Junctionless Transistors

Using extensive numerical device simulation, we investigate the influence of sidewall spacers on the analog/RF performance of double-gate junctionless transistors at channel length of 30 nm. Our findings reveal that peak transconductance and peak intrinsic gain increase by 5.2 and 71.3% for spacer dielectric constant k = 30 as compared to the respective values for k = 3.9, while peak unity gain cut-off frequency increases by 37% for k = 3.9 compared with the value for k = 30. The transconductance generation factor is found to be less sensitive to the variation in k. With increasing k the output conductance becomes less for low gate overdrive voltage V _GT while it shows a reverse trend for higher V _GT. It is evident from our studies that peak transconductance, peak transconductance generation factor, peak gain, and peak cut-off frequency increase by 13, 10, 27, and 20%, respectively, for spacer length of 5 nm compared with the corresponding values for spacer length of 15 nm. However, with a larger spacer length, the output conductance exhibits reduced value for lower V _GT, while it becomes comparable with the values for smaller spacer lengths as V _GT increases.