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Published in:
2010 | OriginalPaper | Chapter
Implementation of ADPLL with 0.6μm CMOS Process for SOC Applications
Authors : V. Leela Rani, V. Suma Latha, G. T. Rao, D. S. Murty
Published in: Recent Trends in Networks and Communications
Publisher: Springer Berlin Heidelberg
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In this paper, we propose a new All Digital Phase Locked Loop (ADPLL) for SOC applications. The proposed ADPLL can be designed with any standard cell library. The ADPLL has been implemented using standard cells of 0.6μm CMOS process from CADENCE TOOLS. The designed ADPLL operates in the range between 12.5 MHz to 100MHz with phase error of less than 10ns. Portability over different processes is ensured in the new ADPLL. The complexity in the design process is reduced. The time for redesign considerably decreases making it suitable for SOC applications.