Skip to main content
Top
Published in:
Cover of the book

2012 | OriginalPaper | Chapter

1. Introduction

Authors : Pierre-Emmanuel Gaillardon, Ian O’Connor, Fabien Clermidy

Published in: Disruptive Logic Architectures and Technologies

Publisher: Springer New York

Activate our intelligent search to find suitable subject content or patents.

search-config
loading …

Abstract

In this chapter, we aim to introduce the global context of the book. While the microelectronics industry is still lead by the scaling, we point out its limits and highlights some novel way coming from the nanotechnologies. In order to provide an efficient evaluation strategy of the different ways, we present the global methodology used in the remaining of the book.

Dont have a licence yet? Then find out more about our products and how to get one now:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

  • über 102.000 Bücher
  • über 537 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Maschinenbau + Werkstoffe
  • Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 390 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Maschinenbau + Werkstoffe




 

Jetzt Wissensvorsprung sichern!

Footnotes
1
This term was first coined at the 100 k transistor mark. Other terms were later proposed (e.g. ULSI) to reflect the continually increasing complexity of integrated circuits , but  remains the term of choice within the community.
 
2
High Threshold Voltage (Vt).
 
3
Low Threshold Voltage (Vt).
 
Literature
1.
go back to reference J. Bardeen, W.H. Brattain, Three-electrode circuit element utilizing semiconductor materials, US Patent No. 2524035 (1948) J. Bardeen, W.H. Brattain, Three-electrode circuit element utilizing semiconductor materials, US Patent No. 2524035 (1948)
2.
go back to reference D. Kahng, Electric field controlled semiconductor device, US Patent No. 2524035 (1960) D. Kahng, Electric field controlled semiconductor device, US Patent No. 2524035 (1960)
3.
go back to reference G.E. Moore, Cramming more components onto integrated circuits, Electronics 38(8), 114–117 (1965) G.E. Moore, Cramming more components onto integrated circuits, Electronics 38(8), 114–117 (1965)
4.
go back to reference H. Iwai, Roadmap for 22 nm and beyond (Invited Paper). Microelectron. Eng. 86(7–9), 1520–1528 (2009) H. Iwai, Roadmap for 22 nm and beyond (Invited Paper). Microelectron. Eng. 86(7–9), 1520–1528 (2009)
5.
go back to reference T. Hoffmann, G. Doorribos, I. Ferain, N. Collaert, P. Zimmerman, M. Goodwin, R. Rooyackers, A. Kottantharayil, Y. Yim, A. Dixit, K. De Meyer, M. Jurczak, S. Biesemans, GIDL (gate-induced drain leakage) and parasitic schottky barrier leakage elimination in aggressively scaled HfO2/TiN FinFET devices, IEDM Tech. Dig. 725–728 (Dec 2005) T. Hoffmann, G. Doorribos, I. Ferain, N. Collaert, P. Zimmerman, M. Goodwin, R. Rooyackers, A. Kottantharayil, Y. Yim, A. Dixit, K. De Meyer, M. Jurczak, S. Biesemans, GIDL (gate-induced drain leakage) and parasitic schottky barrier leakage elimination in aggressively scaled HfO2/TiN FinFET devices, IEDM Tech. Dig. 725–728 (Dec 2005)
6.
go back to reference T. Hori, Drain-structure design for reduced band-to-band and band-todefect tunneling leakage, VLSI Technol. Symp. Tech. Dig. 69–70 (June 1990) T. Hori, Drain-structure design for reduced band-to-band and band-todefect tunneling leakage, VLSI Technol. Symp. Tech. Dig. 69–70 (June 1990)
7.
go back to reference R.H. Dennard, F.H. Gaensslen, H.-N. Yu, V.L. Rideout, E. Bassous, A.R. Leblanc, Design of ion-implanted MOSFET’s with very small physical dimensions. IEEE J. Solid State Circuits 9(5), 256–268 (1974)CrossRef R.H. Dennard, F.H. Gaensslen, H.-N. Yu, V.L. Rideout, E. Bassous, A.R. Leblanc, Design of ion-implanted MOSFET’s with very small physical dimensions. IEEE J. Solid State Circuits 9(5), 256–268 (1974)CrossRef
Metadata
Title
Introduction
Authors
Pierre-Emmanuel Gaillardon
Ian O’Connor
Fabien Clermidy
Copyright Year
2012
Publisher
Springer New York
DOI
https://doi.org/10.1007/978-1-4614-3058-2_1