Journal of Electronic Testing

Editorial

Vishwani D. Agrawal

Test Technology Newsletter

Reducing Library Characterization Time for Cell-aware Test while Maintaining Test Quality

Zhan Gao, Min-Chun Hu, Santosh Malagi, Joe Swenton, Jos Huisken, Kees Goossens, Erik Jan Marinissen

A Low-Cost, Robust and Tolerant, Digital Scheme for Post-Bond Testing and Diagnosis of TSVs

Vasileios Gerakis, Yiorgos Tsiatouhas, Alkis Hatzopoulos

A Cascaded Multicasting Architecture for Test Data Compression

Wang-Dauh Tseng

Fault Diagnosis Method of Low Noise Amplifier Based on Support Vector Machine and Hidden Markov Model

Lu Sun, Yang Li, Han Du, Peipei Liang, Fushun Nian

Evaluation of a Two-Tier Adaptive Indirect Test Flow for a Front-End RF Circuit

H. El Badawi, F. Azais, S. Bernard, M. Comte, V. Kerzerho, F. Lefevre

Tolerating Soft Errors with Horizontal-Vertical-Diagonal-N-Queen (HVDNQ) Parity

Muhammad Sheikh Sadi, Sumaiya Sumaiya, Mouly Dewan, Atikur Rahman

Radiation Tolerant SRAM Cell Design in 65nm Technology

JianAn Wang, Xue Wu, Haonan Tian, Lixiang Li, Shuting Shi, Li Chen

Soft Errors Sensitivity of SRAM Cells in Hold, Write, Read and Half-Selected Conditions

Cleiton Magano Marques, Cristina Meinhardt, Paulo Francisco Butzen

Single Event Upset Evaluation for a 28-nm FDSOI SRAM Type Buffer in an ARM Processor

Shuting Shi, Rui Chen, Rui Liu, Mo Chen, Chen Shen, Xuantian Li, Haonan Tian, Li Chen

Method of Implanting Hardware Trojan Based on EHW in Part of Circuit

Lijun Liu, Tao Wang, Xiaohan Wang