Leakage Reduction in Full Adder Circuit Using Source Biasing at 45 nm Technology

In this paper, a new technique of source biasing is proposed for leakage reduction in CMOS full adder (FA) circuit. It includes tail transistor between pull-down network and ground (GND). The source terminal of tail transistor is connected to GND during active mode and will be at Vdd in idle mode. High potential at source of tail transistor reduces the potential difference between source and drain of NMOS transistors which reduces gate leakage current. The proposed approach does not have the problem of ground bounce noise (GBN) during idle-to-active mode of transition. The proposed new technique is having reduction in leakage power up to 72% as compared to the existing FA circuit and peak power reduces up to 37% as compared to existing FA circuit while keeping other performance parameters in acceptable range.