Logarithmic Voltage-to-Time Converter for Analog-to-Digital Signal Conversion

Data converters are a fundamental building block for many circuits. Application examples of data converters include digitizing voice, image, and wireless telecommunications signals. Data converters are used because it is easier to process a digital quantity than to perform the equivalent processing in the analog domain. Without them it would not be possible to have devices such as digital audio and video broadcast, digital cameras and mobile phones. Usually the converters employed in those applications have a linear scale, and for most applications that is the proper choice, however, for some applications a nonlinear conversion scale may be more appropriate.

There are several analog-to-digital converter architectures described in the literature that implement a nonlinear conversion characteristic. This chapter presents an overview of the different architectures and how the nonlinear characteristic is achieved and summarizes the state-of-the-art for each of the architectures. Most of the architectures described in the following sections can be used to implement arbitrary nonlinear transfer characteristics, however most of the examples found in the literature show logarithmic transfer functions. For the same conversion resolution, a logarithmic converter can attain a larger input dynamic range than a linear converter, conversely for linear and logarithmic converters with a similar input dynamic range, the logarithmic converter will attain a smaller signal to noise ratio. Figure 2.1 shows an example of a conversion result of a sinusoidal signal by converters with different conversions characteristics. On the left, the conversion result for a linear converter shows a constant quantization step while for the other two converters the quantization step is not constant. The floating-point converter is characterized by having zones with a constant quantization step, with the quantization step being different from zone to zone. The logarithmic converter on the other hand does not have a fixed quantization step like the linear converter, or zones where the quantization step is fixed like in the floating-point converter. In the logarithmic converter the quantization step increases progressively from a small quantization step for small input signals to a large quantization step for large input signals.

This Chapter presents a novel logarithmic analog-to-digital conversion architecture comprising a time-to-digital converter and voltage-to-time conversion elements based on cross-coupled inverters. The voltage-to-time conversion element with a logarithmic conversion characteristic and the main sources of nonlinearity will be studied in this Chapter.

This Chapter will present the design of two logarithmic voltage-to-time conversion elements. Both options analyzed in the previous chapter, conversion elements with and without degeneration resistors, will be designed. The design will be performed using the equations derived in the previous chapter. Simulation results for process corners, offset and Monte Carlo will be presented at the end of the chapter.

This chapter will present the major building blocks that comprise the demonstrator prototype. Except for the I/O pads there was no use of ready-made cells, everything had to be designed from schematic capture to the final layout. Table 5.1 summarizes the logic cells and logic blocks that have been designed. Most of the blocks have been used in the design of the test chip however some blocks such as the static flip-flop with reset and the 10 bit frequency counter have not been used. The unused blocks are leftovers from previous iterations of the test chip where different testing methodologies were being evaluated.

This Chapter details the custom hardware test platform and test software that was developed to evaluate the demonstrator prototype. Experimental results will be presented and compared with the simulation results obtained previously. The experimental results will also be compared with other converters presented in the literature, both logarithmic converters and linear converter.

This chapter will present the future research work direction regarding calibration and architecture improvements. Two possible calibration schemes are presented and their advantages and drawbacks are discussed. A conversion architecture that solves the shortcomings identified in the architecture presented in this thesis is presented and its mode of operation is detailed. The concluding remarks will be drawn at the end of the chapter.