Logic Synthesis

Chapter 2 has already outhned the main concepts and techniques behind our approach to the design of asynchronous control circuits. The key stage in this approach is logic synthesis from Signal Transition Graphs (STGs), a model which offers important advantages to the asynchronous controller and interface designer. On one hand, STGs are very similar to Timing Diagrams, which can be seen as a conventional pragmatic design notation. On the other hand, they are based on the formally sound theory of Petri nets, with a clearly defined syntax and semantics, and a plethora of algorithms and techniques for model analysis and transformations.