3. Low Power Strategies

This chapter presents architectural considerations for the proposed transceiver. Four main aspects are identified as essential for ultra-low power consumption. First, the definition of the receiver architecture is a fundamental issue as it affects the structure and design requirements of individual blocks. Second, the number of active RF blocks has to be minimized in order to end up with as few RF nodes as possible. Third, the impedance of internal RF nodes has to be maximized in order to relax the power demand of the driven blocks. Finally, a low-complexity demodulation scheme avoiding quadrature multi-bit analog-to-digital converters (ADCs) is needed. Based on the above discussions, the proposed transceiver employs a passive zero-IF RX front-end and a TX with direct VCO modulation, which includes a step up transformer to rise the antenna impedance and a phase-domain ADC (Ph-ADC) which only needs only four bits of resolution to demodulate the incoming signal.