Mapping Hybrid Traffic Shaper Architecture To FPGA Design For TSN Applications

This chapter explores the mapping of hybrid traffic shaper architectures to FPGA designs for Time-Sensitive Networking (TSN) applications. It begins by introducing TSN and its importance in enabling real-time, deterministic communication over Ethernet networks. The chapter then delves into various traffic shaper architectures, including Time Aware Shaper (TAS), Credit Based Shaper (CBS), and Asynchronous Traffic Shaper (ATS), and their individual performances. The main focus is on the hybrid architecture that combines TAS, CBS, and ATS, highlighting its advantages in terms of low latency, minimal backlog, and reduced jitter. The chapter also discusses the implementation of this hybrid architecture on FPGAs, detailing the RTL modules involved and the performance results. It concludes by discussing the potential applications of this architecture in various industries and suggests future enhancements. The chapter provides a comprehensive review of TSN traffic shaper architectures and their implementation on FPGAs, making it a valuable resource for professionals seeking to understand and implement these technologies in real-time communication systems.