Mapping of Subtractor and Adder-Subtractor Circuits on Reversible Quantum Gates

Reversible arithmetic units such as adders, subtractors and comparators form the essential components of any hardware implementation of quantum algorithms such as Shor’s factoring algorithm. Further, the synthesis methods proposed in the existing literature for reversible circuits target combinational and sequential circuits in general and are not suitable for synthesis of reversible arithmetic units. In this paper, we present several design methodologies for reversible subtractor and reversible adder-subtractor circuits, and a framework for synthesizing reversible arithmetic circuits. Three different design methodologies are proposed for the design of reversible ripple borrow subtractor that vary in terms of optimization of metrics such as ancilla inputs, garbage outputs, quantum cost and delay. The first approach follows the traditional ripple carry approach while the other two use the properties that the subtraction operation can be defined as \(a-b\) = \(\overline{\bar{a}+b}\) and \(a-b\) = \({a+\bar{b}+1}\), respectively. Next, we derive methodologies adapting the subtractor to also perform addition as selected with a control signal. Finally, a new synthesis framework for automatic generation of reversible arithmetic circuits optimizing the metrics of ancilla inputs, garbage outputs, quantum cost and the delay is presented that integrates the various methodologies described in our work.