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2016 | Book

Memristor-Based Nanoelectronic Computing Circuits and Architectures

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About this book

This book considers the design and development of nanoelectronic computing circuits, systems and architectures focusing particularly on memristors, which represent one of today’s latest technology breakthroughs in nanoelectronics. The book studies, explores, and addresses the related challenges and proposes solutions for the smooth transition from conventional circuit technologies to emerging computing memristive nanotechnologies. Its content spans from fundamental device modeling to emerging storage system architectures and novel circuit design methodologies, targeting advanced non-conventional analog/digital massively parallel computational structures. Several new results on memristor modeling, memristive interconnections, logic circuit design, memory circuit architectures, computer arithmetic systems, simulation software tools, and applications of memristors in computing are presented. High-density memristive data storage combined with memristive circuit-design paradigms and computational tools applied to solve NP-hard artificial intelligence problems, as well as memristive arithmetic-logic units, certainly pave the way for a very promising memristive era in future electronic systems. Furthermore, these graph-based NP-hard problems are solved on memristive networks, and coupled with Cellular Automata (CA)-inspired computational schemes that enable computation within memory. All chapters are written in an accessible manner and are lavishly illustrated. The book constitutes an informative cornerstone for young scientists and a comprehensive reference to the experienced reader, hoping to stimulate further research on memristive devices, circuits, and systems.

Table of Contents

Frontmatter
Chapter 1. Memristor Fundamentals
Abstract
The memristor is considered one of the most promising nano-devices among those currently being studied for possible use in electronic systems of the future. The best performance features which have been demonstrated in published experimental results regarding research device prototypes so far include fast switching speed, high endurance and data retention, low power consumption, high integration density, and (perhaps most importantly) CMOS compatibility. Undoubtedly, the combination of such advantageous characteristics in a single device justifies the phenomenal research interest that resistance-switching devices have generally attracted over the last few years and verify the existing rumors about their potential application in both storage and processing units of future electronic systems. Memristive nano-devices are the focus of this book and this chapter aims to introduce the reader to their fundamental properties on which the presented study is based.
Ioannis Vourkas, Georgios Ch. Sirakoulis
Chapter 2. Memristor Modeling
Abstract
This chapter presents a SPICE-compatible device model of a voltage-controlled bipolar memristor which explains memristive behavior while primarily attributing the switching effect to an effective tunneling distance modulation. This model satisfies the desired memristive fingerprints and involves significantly low-complexity operation under an unlimited set of frequencies over a wide range of applied voltages. The SPICE simulation results are found in good qualitative and quantitative agreement with the theoretical formulation of the model. Also, the model represents well the complex switching behavior of memristor when fitted to other widely used published models. Therefore, it can be used to provide accurate enough circuit simulations for a wide range of memristor devices and voltage inputs, while it can be incorporated as a circuit element in any current computer-aided design work.
Ioannis Vourkas, Georgios Ch. Sirakoulis
Chapter 3. Dynamic Response of Multiple Interconnected Memristors
Abstract
This chapter focuses on the architectural perspectives that arise in circuits with multiple interconnected memristors, which demonstrate threshold-dependent switching behavior. We investigate the dynamic switching response and analyze the characteristics of both regular and irregular serial/parallel memristive circuit compositions; i.e. memristive combinations which are structured using either repetitive or non-repetitive interconnection patterns. We show how composite memristive systems can be efficiently built out of individual memristors, presenting different electrical characteristics from their structural elements. Following the proposed generalized synthesis concept, by appropriately selecting and interconnecting the constitutive circuit components, we construct composite memristive systems which exhibit behavior of programmable multi-state conducting elements. We provide several examples of such memristive implementations, combining different polarities and different initial states and/or switching characteristics, thus causing highly nontrivial, composite responses to the applied voltages. Finally, we present a novel approach for the construction of robust fine-resolution pro-grammable memristive switches.
Ioannis Vourkas, Georgios Ch. Sirakoulis
Chapter 4. Memristor-Based Logic Circuits
Abstract
Amongst several emergent applications of the memristance switching phenomenon, the implementation of logic circuits is gaining considerable attention. Memristor-based logic circuits open new pathways for the exploration of advanced computing architectures as promising alternatives to conventional integrated circuit technologies. However, up to now no standard logic design methodology exists, since it is not immediately clear what kind of computing architectures would in practice benefit the most from the computing capabilities of memristors. This chapter addresses memristive logic circuit design and computational methodologies, aiming to approach this novel area of research while motivating for further research on innovative design strategies, which comply with emerging technologies. First, a summary of the most recognized memristive logic circuit design concepts is provided. Then two novel logic design paradigms are presented, which aim to address several drawbacks of other existing design concepts in the literature, and to facilitate the incorporation of memristors in currently established logic circuit architectures. Thus they could be promising candidates to be used in future electronic systems design. The proposed design paradigms are validated through SPICE-based simulations for a variety of complex combinational logic circuits.
Ioannis Vourkas, Georgios Ch. Sirakoulis
Chapter 5. Memristive Crossbar-Based Nonvolatile Memory
Abstract
Among several types of emerging memory technologies, memristor-based nonvolatile resistive RAM (ReRAM) is currently being investigated as a promising candidate to potentially replace the popular Flash memories, and even other conventional memories such as SRAM and DRAM. At the architectural level, crossbar cell array structure is considered one of the best ways to implement memristor-based ReRAM. This chapter presents an overview of promising ReRAM technologies, their potential benefits, and the key research challenges, with a focus on reduction/oxidation (Redox)-based RAM. It briefly describes the basic operation principles of memristive memory cells, and presents the memristor-based crossbar memory architecture to finally focus on the serious negative impact of the current sneak-paths. Then, two possible methodologies are explored as means to deal with the sneak-path problem, concerning (i) novel storage cell structures, and (ii) modifications in the memory architecture. More specifically, (i) anti-parallel memristive switches are studied as potential cross-point elements in ReRAM arrays, in comparison with anti-serial (complementary) memristive switches. A comprehensive and comparative presentation between them is provided, while commenting on their overall performance and the most appropriate switching characteristics that the structural memristors should have, in order to better fit to memory applications. Moreover, (ii) five alternative architectures (topologies) for passive crossbar ReRAM are presented, which are based on the introduction of a certain percentage of insulating nodes spread out inside the array according to specific distribution patterns. Both approaches enable crossbar memory arrays without select devices, thus they simplify the array fabrication process and could be well-suited for future data storage applications. Finally, XbarSim, a GUI-based educational simulation tool aiming to serve students/researchers who wish to explore and study the memristive crossbar circuit architecture, is presented.
Ioannis Vourkas, Georgios Ch. Sirakoulis
Chapter 6. High-Radix Arithmetic-Logic Unit (ALU) Based on Memristors
Abstract
This chapter presents a novel method for implementing crossbar-based multi-level memories, where each cross-point cell stores multiple bits. Furthermore, a conceptual solution for novel CMOS-compatible, memristive, high-radix arithmetic logic units (ALUs) is proposed, for future computing systems. More specifically, a hybrid ALU circuit nano-architecture is described, where: (a) CMOS peripheral circuits are used for binary arithmetic operations; (b) a memristive reconfigurable crossbar-based memory block is used to: (i) allow parallel read/write of data; (ii) facilitate the implementation of efficient arithmetic algorithms (e.g. fast partial product creation for multiplication); and (iii) store information in a compact, high-radix form. Instead of single memristors, the crossbar nodes comprise a type of multi-state composite memristive switches, described in Chap. 3, which permit multi-bit storage in a more robust manner. Radix-4 representation is used because: (i) it balances the offered advantages with the peripheral binary conversion circuitry overhead; and (ii) it provides a good density/reliability trade-off. The fine operation and accuracy of the proposed system architecture is demonstrated through SPICE-level simulations.
Ioannis Vourkas, Georgios Ch. Sirakoulis
Chapter 7. Networks of Memristors and Memristive Components
Abstract
Memristors demonstrate a natural basis for computation that combines information processing and storage in the memory itself. A very powerful and promising memristor-based computing structure, which implements analog parallel computations, is the memristor network. In such structure there is continuous information exchange during calculations which renders a tremendous increase of computational power due to the massively parallel network dynamics. In this chapter we explore this computing concept via numerical and circuit simulations for the purpose of investigating the network dynamics, utilizing the well-documented physics of single devices and known network topologies. We address two of the probably most well-known inherently complex problems, in terms of computation time, i.e. the shortest path and the maze-solving problems, via computations in memristor networks. For these specific problems we further extend already proposed memristor network-based computing approaches by introducing certain modifications in the computing platform. Several scenarios are examined considering also the inclusion of devices with different switching characteristics in the same computation. Additionally, we address the appropriate mapping issue of graph-based computational problems via a novel modeling approach, which is based on specific circuit models describing several types of edges connecting the graph vertices. The emergence of new functionalities opens doors to exciting new computing concepts and encourages the development of parallel memristive computing systems.
Ioannis Vourkas, Georgios Ch. Sirakoulis
Chapter 8. Memristive Computing for NP-Hard AI Problems
Abstract
Reported properties of network configurations of memristors, as presented in Chap. 7, showed that composite memristive systems significantly improve the efficiency of logic operations via massive analog parallelism. The sparse nature of such network-based computations, though, resembles certain operational features and computing capabilities of Cellular Automata (CA), a powerful parallel computational model which leads to scalable hardware (HW) architectures with very high device densities. When CA-based models are implemented in HW, the circuit design reduces to the design of a single cell and the overall layout results regular with exclusively local inter-connections. Moreover, the models are executed fast by exploiting the parallelism of the CA structure. This chapter focuses on a circuit-level CA-inspired approach for in-memory computing schemes using memristors and composite memristive components. A generalized CA cell circuit design methodology is described, which facilitates the implementation of CA-based computing algorithms, exploiting the threshold-type resistance switching behavior of memristors and of multi-state memristive components. Several CA cell example structures are designed and employed in array-like circuit geometries, where computations regarding classic NP-hard problems of various areas of artificial intelligence (AI) take place. The main contribution of this methodology consists in the combination of unconventional computing with CA and the unique circuit properties of memristors, aiming to set off parallel computing capabilities and improve CA-based hardware accelerators for NP-hard AI problems.
Ioannis Vourkas, Georgios Ch. Sirakoulis
Metadata
Title
Memristor-Based Nanoelectronic Computing Circuits and Architectures
Authors
Ioannis Vourkas
Georgios Ch. Sirakoulis
Copyright Year
2016
Electronic ISBN
978-3-319-22647-7
Print ISBN
978-3-319-22646-0
DOI
https://doi.org/10.1007/978-3-319-22647-7