Micro and Nanoelectronics Devices, Circuits and Systems

New generation Radio Frequency Microelectromechanical Systems (RF MEMS) Switches with high performance have been developed recently and the capability to exploit them for designing reconfigurable antennas is presented in this paper. A parasitic antenna on a planar structure with the Yagi-Uda concept is used as a proof of concept. The structure is composed of a dipole of half the wavelength of the operational frequency (the driven element) and a set of parallel parasitic elements on the sides that are exploited to tune the antenna characteristics. Four antenna configurations are obtained by adjusting the length of the parasitic elements using RF MEMS switches placed at suitable discontinuities. The preliminary results demonstrated that the considered antenna structure (operating in the X-band) is able to steer the beam from broadside to end fire pattern keeping a return loss below −10 dB and a good gain in all the antenna configurations.

This paper aims to compare the performance of miller compensated two-stage operational transconductance amplifier using FinFET and bulk CMOS technologies. Simulations have been performed in SPICE to analyze performance parameters using Predictive Technology Model (PTM) of 16-nm FinFET and 22-nm bulk CMOS from Arizona State University for same supply voltage of 1.1 V, common-mode voltage of 0.6 V and input bias current of 5 µA. The CMOS process showed open loop DC gain of 53.05 dB, Unity Gain Bandwidth (UGB) of 208.62 MHz, Phase Margin of 68.66° and Gain Margin of 14.53 dB, whereas comparative analysis with FinFET demonstrates an improvement of 33.6% in DC gain and 85.93% in Unity Gain Bandwidth with Phase Margin of 80.47° and Gain Margin of 18.10 dB. In terms of Power Supply Rejection (PSR), the FinFET Technology outperformed that of CMOS technology by 1.53 dB.

The study on organic electronics attracted the researcher and the industrialist for its novel features. In this paper, a comparative analysis has been performed for the single- and the dual-gatebased organic thin-film transistors (OTFTs) to examine the performance parameters such as on/off current ratio, subthreshold swing, mobility, and threshold voltage, etc. The analytical modeling and simulation have been carried out with the help of the ATLAS 2D numerical device simulator, and it is observed that the variation in the structural dimension of the OTFT is widely affecting these performance parameters. Furthermore, it is also observed that the reduction in the channel length by 80% (from 50 µm to 10 µm having a step size = 10) leads to an increase in the drive current by 81% in the dual-gatebased OTFT and 80% in the case of single-gatebased OTFTs, respectively, and the variation in thickness of active layer from 60 nm to 20 nm (under the same step size) leads to an enhancement in the on/off current ratio by 99% with the subsequent reduction in leakage current. Decreasing the dielectric thickness from 10 nm to 2 nm (with a step size of 2) leads to an enhancement in these performance parameters. Finally, it is witnessed that the dual-gate OTFT is showing excellent performance over single-gate OTFT, which sanctions to achieve high-speed applications.

In this paper, we have investigated undoped and indium-doped titanium dioxide (TiO2) nanoparticles prepared using sol–gel method. The aim of this work is to analyse the effect of indium incorporation on the structure and morphology of the materials. X-ray diffraction (XRD) pattern reveals a significant influence of In-doping on crystallinity and average grain size of the TiO2 nanoparticles. The morphology of the nanoparticles analysed using transmission electron microscopy (TEM) and scanning electron microscopy (SEM) images confirms the formation of spherical- and triangular-shaped nanoparticles with large surface area. Further, study of TEM images confirmed the obtained XRD results. Moreover, X-ray photoelectron spectroscopy (XPS) and electron diffraction spectroscopy (EDS) approve the electronic states and composition of all different chemicals existing in the samples. All the results are found and verified with the literature.

Tunnel field effect transistor (TFET) is considered as the probable successor of traditional MOSFET and has gained lots of concentration for ultralow-power application because of lower OFF current and steep switching mechanism. Instead of using thermionic conduction like MOSFET, it operates under gate-controlled band-to-band tunneling mechanism. This paper reviews different structures of TFET, modeling available for design and parameters like speed, ION /IOFF ratio, power consumption, subthreshold swing, etc., which replaces the conventional MOSFET for greater efficiency.

We report a defective 1D photonic crystal for real-time sensing of blood hemoglobin concentrations. The proposed structure is configured as adjacent thin films of Na3AlF6 and ZnSe including a defect remain at the middle. The cornerstone of this research is based on the analysis of the transmission spectrum by manipulating the transfer matrix method (TMM). Upon infiltrating the defect layer with blood containing different hemoglobin concentrations, the shift in the resonant mode wavelength is observed within the photonic band gap (PBG). Sensor performance is evaluated by varying the incident light angle and thickness of the defect medium. Numerous sensing characteristics such as sensitivity, figure of merit and signal-to-noise ratio are computed for studying the effectiveness of the proposed sensor. Additionally, the simple structure with notable sensing performance makes the proposed sensor a suitable candidate for biosensing applications.

Basically, next-generation powerful building blocks are represented using semiconductor nanowires. These semiconductor nanowires have attractive properties, and along with that, they have bio-molecules, high surface-to-volume ratios, and nanometer scale footprint comparable to sub-cellular structures. Hence, in this article, the field of nanowire bioelectronics is discussed in a detailed manner and also summarizes the recent progress of nanowire bioelectronics. This article mainly focuses on the four types of biosensors they are, planar biosensor, cylindrical biosensor, DGFET, and EGFET. Each biosensor is discussed in a detailed manner and results re-obtained from the nanowire bioelectronics.

In this work, low-frequency noise behavior is studied for a proposed dual dielectric spacer-based heterojunction double-gate PNPN TFET structure. Electrical parameters of the proposed structure are investigated with regard to ION (ON-state current), IOFF (OFF-state current), and SS (subthreshold swing). Noise quantity, such as noise spectral density in terms of current (SID, unit A2/Hz) and voltage (SVG, unit V2/Hz), is studied for different trap conditions and different mole fractions, lengths, and doping concentrations of the pocket material. The study reveals that the pocket parameters have a significant influence on the noise behavior of the proposed structure.

In this work, the effect of replacing traditional indium tin oxide (ITO) anode with different anode materials is reported. The detailed simulation is conducted on organic light-emitting diode (OLED) consisting of commonly used emissive or organic layers with tris(8-hydroxyquinoline) aluminum (Alq3) at an operating wavelength of 540 nm. Different device simulations using aluminum zinc oxide (AZO), zinc mono-oxide (ZnO), graphene (7 nm/12 nm), and silver (Ag) anode materials with different work functions are modelled and simulated. For measuring OLED's optical results, the finite difference time domain (FDTD) approach was used. The angular distribution of OLEDs with reference to viewing angle with different anodes is reported. The results show the optical effects of the anode material with Graphene has better enhancement in light output compared to other materials. This work shows the far field contours of all the anode materials that improve light production and that optimum emission from an OLED to check the alternative to indium tin oxide anode material.

A surface plasmon resonance waveguide sensor operating in the visible wavelength range is presented for refractive index-based sensing. The silver material is used because of its chemical stability and its strong electromagnetic fields on surface of the nanoparticle. The simulation and modeling of surface plasmon resonance sensor are discussed. The aluminum oxide surface coating material improves the resonance of the sensor because of its stable material properties in optical and chemical application. The three modes of the sensor discussed here are transfer electric, transfer magnetic and the surface plasmon waveguide mode. The effective index value of 1.5178 is observed for the surface plasmon mode of the SPR waveguide sensor. The attenuation loss of 21 dB/cm is obtained at visible wavelength. The sensitivity when averaged for two analyte refractive index is 354 nm/refractive index unit (RIU). The proposed surface plasmons resonance sensor is used as refractive index-based sensor for environmental and chemical monitoring. This proposed work can be used to sense analyte refractive index based on the variation of the change in the resonant wavelength.

In this paper, we have investigated high isolation and low actuation voltage offering triangular membrane-based shunt capacitive RF MEMS switch. Unlike conventional analysis, here we have extended the switch design up to the packaging stage. The triangular membrane is designed with slot and perforation. The triangular membrane is micromachined with a gold (Au) thickness of 0.5 µm, the air gap is 3 µm, and the eventually required actuation voltage is 2.4 V. The membrane resonant frequency is 57.5 kHz. Because of the incorporation of multiple triangular membranes (M1 and M2) and HfO2 as a dielectric material, the switch is offering high isolation of −80 dB. The overall switch has six pins, i.e., RFin, RFout, VB1, VB2, GND1, and GND2.

This work investigates the effect of Bragg’s reflector configuration stages and its material on the performance of flexible FBAR sensor. Bragg’s reflector configuration has been formed with various high and low acoustic Impedance layers such as Mo/SiO2, W/SiO2, and W/Al. The detailed investigation of flexible FBAR sensor has been done using 2-D finite element method (FEM) simulations performed on COMSOL Multiphysics software. Acoustic impedance versus frequency and frequency versus quality factor plots were drawn for the detailed investigation of material and number of Bragg’s reflector configuration stages on the performance of the flexible FBAR sensor. The comparative results for various Bragg’s reflector configurations have been summarized and reported. It is reported that spurious modes were present while using even number of stages to form Bragg’s reflector configuration. Thus, to remove spurious harmonic modes odd number of Bragg’s reflector configuration stages are required. The present work also states that W/SiO2-based Bragg’s reflector configurations are best suited to achieve enhanced performance in terms of enhanced coupling coefficient and figure of merit. This investigation offers new framework for the design of a flexible FBAR sensor with high performance.

A predictive analysis of step-quantum well (SQW) active region (AR) for quantum cascade detectors (QCDs) has been performed. Different active well designs using SQW are presented and investigated for QCD performance improvement. A coupled quantum well design is taken for the analysis where the active well is made of SQW. Electron energies and corresponding wavefunctions are calculated by solving the time-independent Schrödinger equation using finite difference method. Different non-radiative scattering rates are calculated, and further, the escape probability of photoexcited carriers from the active well is predicted. The effect of step-barrier width on the oscillator strength of optical transition in the SQW has been investigated. The effect of step-barrier width on the non-radiative transition rates in the active well as well as escape probability from the active well has been further investigated. It is observed that SQW ARs provide higher escape probability by reducing non-radiative scattering rates of photoexcited carriers back into the active well; therefore, improved responsivity performance can be achieved. The escape probability has been analyzed for different operating temperatures. It is also observed that by using SQW as the AR, a higher barrier thickness can be achieved without degrading the responsivity performance significantly. A higher barrier thickness gives higher thermal resistance, hence higher detectivity performance.

At present, more than half the chip area is occupied by memory. So, it becomes imperative to find an efficient design of memory and deal with issues of power, delay, and reliability. A significant amount of memory delay is caused by its decoder. The optimized decoder used in this paper is faster than the conventional decoder by approximately 80% and consumes 92% lesser power. In this paper, four types of decoders are discussed with their performance comparison. A pre-charge pulse generator is also used in the design to pull up the bit-lines before performing the read operation. This paper aims to provide the optimal design of static random-access memory (SRAM) and an efficient address decoder. In the quest for efficient design, the focus remains on reducing total transistor counts and their optimum sizing.

The pre-scalers are extensively used in high-speed multi-GHz applications to scale down the high frequencies before it reaches to the frequency divider block of a frequency synthesizer. In this paper, a new approach to design the metal–oxide–semiconductor CML (MCML) pre-scaler compliant with the 5G communication standard is presented. A hand calculation-based general analysis is shown in this work. A couple of delay cells have been introduced in the proposed architecture, and the theoretical foundations of the design approach have been established analytically. An MCML divide-by-5 pre-scaler is designed following the proposed design approach.

The reducing agents and their concentrations used during the synthesis of graphene aerogel (rGO, i.e., reduced graphene oxide) highly effect the chemical characteristics and gas sensing properties of the resulted material. Therefore, in this paper, in order to investigate their effect on gas sensing properties of graphene aerogel, we have synthesized graphene aerogel using three different reducing agents, i.e., thio urea, ammonia, and ethylene glycol. Further, to study the effect of reducing agent’s weight ratio/concentration on the properties, we have used three different weight amounts of thio urea. In total five rGO samples were synthesized and characterized. In order to investigate their gas sensing properties, the gas sensing response characteristics of all five rGO samples were recorded toward 100 ppm ammonia concentration at room temperature. It is found that the two rGO samples, i.e., ammonia-treated rGO aerogel and thio urea-treated rGO aerogel (300 mg), show good gas sensing response toward 100 ppm concentration of ammonia gas (1.4% and 1.21%, respectively) at room temperature, while remaining three samples’ gas sensing responses were very poor (0.102%, 0.205%, and 0.640%).

In this study, a double-gate tunnel field-effect transistor with germanium epitaxial tunnel layer (Ge ETL-DGTFET) combining line tunneling orientation was proposed. This CMOS process compatible structure shows better performance in terms of ON-state current and subthreshold swing than silicon-based ETL-DGTFET and GOSO TFET due to the low bandgap ETL region. It exhibits an average subthreshold swing (SSavg) of 30 mV/decade and ION of 0.7 mA/µm. Furthermore, the simulation results show a high cut-off frequency (fT) of 65 GHz, a decent intrinsic delay of 3 pSec, and an energy-delay product (EDP) of 0.006 fJ.nS/µm at a supply voltage (VDD) of 0.7 V. The design concept and effect of design parameters on the device performance are thoroughly discussed in this study.

Biosensors are such devices that discover employment in our everyday life in various fields. In this manuscript, we have designed a ferroelectric GaN HEMT biosensor by using the dielectric modulation technique of cavity formation consisting of both ferroelectric layers and biomolecules. Ferroelectric GaN HEMT biosensor is reported for recognization of biomolecules such as protein, streptavidin, chox, and uricase. This work emphasis on the characterization and sensitivity performance of ferroelectric GaN high electron mobility transistor-based biosensor using SILVACO ATLAS software. The immobilization of biomolecules under the gate region results in a large variation of electrostatic properties such as drain current, threshold voltage which can be used as sensing metrics. A significant rise in the drain current with the increasing permittivity value of biomolecule in the nanocavity region. There is a maximum positive shift in threshold voltage that is scrutinized in case of protein as it bears low dielectric constant and also device offers good sensitivity performance.

An increasing demand of on-chip assessment of data in IoT-based devices requires the design of low power on board memory circuits. In this context, a novel 10 T SRAM cell with lower power consumption and improved stability has been design and simulated on 45-nm technology node with cadence virtuoso tool. The loop cutting technique is utilized to improve the stability and minimize the power dissipation of 10 T SRAM cell. It has been noticed that read power consumption is reduced by 11.4% in 10 T SRAM cell as of standard 6 T SRAM cell. The read/write stability is enhanced by 2.4 times/ 2.36 times in comparison with standard 6 T SRAM cell. It occurs because of read decoupled structure. However, the read delay in 10 T SRAM cell is increased by 1.31 times in comparison with six-transistor SRAM cell.

Clustering analysis is considered as one of the most vital analytical techniques for unsupervised machine learning and data mining. The algorithm technique influences the clustering results directly. Clustering has been a widely explored in various application domains such as neural networks, artificial intelligence (AI), statistics, image and video segmentation, and many more. This paper discusses the standard K-means clustering algorithm with its three respective modules: random initialization, training and testing. The work discussed in this paper implements the clustering algorithm in MATLAB tool and then verifies the theoretical results. It also modifies some parts of the algorithm to improve the time and space complexity. Further the algorithm is realized in Verilog and verified in Xilinx ISE tool.

In this work, we report on Heterojunction with intrinsic thin layer-Cu2ZnSnS4 (HIT-CZTS) tandem solar cell modelled using Silvaco TCAD simulator. Initially the HIT and the CZTS solar cells are modelled and validated. Then the tandem structure is designed using HIT as bottom module and CZTS as top module and various loss mechanisms are investigated. From the simulation study, it is revealed that current mismatch among the top and bottom modules has contributed to low short-circuit current density and hence the efficiency of the tandem device. The thickness of CZTS absorber is varied as an attempt to equalize the absorption in top in bottom modules and the performance optimization of the tandem structure is carried out for different tunnelling layers. The tandem structure produces maximum efficiency of 20.93% with Titanium Nitride (TiN) as tunnelling material whereas the maximum efficiency exceeds more than 22% for Si-CZTS tandem solar cell with ITO as tunnelling material. The efficiency can be enhanced further by reducing the overlapping portion of the EQE graph in the tandem structure.

Many of the Internet of things applications are employed on power and resource-constrained devices. Pseudorandom bit generator (PRBG) is one of the crucial components to manage privacy and security on these devices. Among popular PRBGs, linear congruential generator (LCG)-based methods have lower hardware complexity. However, bit sequences generated using single LCG fail to meet the randomness and uniform distribution requirements. In this paper, a triple linear congruential generator (Tri-LCG)-based PRBG method is proposed which can generate pseudorandom bits at uniform clock rate. The proposed method passes 14 tests out of the 15 benchmark tests of NIST standard. Two designs of 8 bits and 24 bits of the proposed Tri-LCG are implemented and synthesized in 45 nm CMOS technology. The proposed designs showed up to 19.87, 14.60 and 38.05% reductions in energy, energy–delay product and area–delay–power product when compared with those of state-of-the-art PRBG methods.

Noise analysis is an important parameter to study the insight of device parameters. At low frequency, mainly flicker noise prevails and effects different performance parameters of a device. This work presents the flicker noise analysis of non-uniform body TFET with dual material source (NUTFET-DMS). The effect of the absence and presence of donor type of interface trap charges at both front and back silicon and gate oxide interface (Si-HfO2 and Si-SiO2) has been incorporated. Further, the analysis also includes the effect of temperature variation (200, 300 and 400 K) in different noise defining parameters such as drain current noise power spectral densities (Sid) and gate voltage noise power spectral densities (Svg). It has been perceived that the occurance of interface trap charges has a unfavorable behavior on both noise power spectral densities (Sid and Svg) mainly at low temperatures. However, when temperature increases, the effect of trap charges becomes negligible, but noise behavior degrades severely.

This paper presents an effect of temperature on small-signal equivalent circuit parameters that have been analyzed for AlInN/AlN/GaN metal-oxide-semiconductor high electron mobility transistor (MOS-HEMT). The analysis has been performed with the temperature range from −50 to 100 °C by S-parameter calculations at 100 GHz frequency. The thermal analysis of equivalent circuit parameters was investigated for the first-time with the proposed device. The equivalent circuit parameters such as intrinsic delay time (τ), gate–source capacitance (Cgs), extrinsic resistances (Rg, Rs, Rd), and intrinsic resistances (Rds, Rgd, Rin) show a positive shift with increasing temperature. On the other hand, intrinsic transconductance (gm), drain–source capacitance (Cds), and gate–drain capacitance (Cgd) show a negative shift with temperature. Obtained results will give some valuable information for design optimizations of GaN-based Monolithic microwave integrated circuits (MMICs) and other high power/frequency applications.

This paper presents a TCAD-based comparative study of vertical power transistors with gallium oxide specifically to FinFET and MOSFET. Also, an electrothermal performance of FinFET and MOSFET is studied with different operating conditions. Semiconductor devices with gallium oxide (Ga2O3) are contemplated to change the applications of power electronics in coming years. There is a possibility to develop Ga2O3-based power semiconductor devices with low on-resistance and large breakdown voltage compared to silicon carbide (SiC)- and silicon (Si)-based devices. The normally off condition can be achieved in FinFET devices by proper Fin design in donor concentration and width. This study will be helpful in analytical model development and fabrication of Ga2O3-based power transistors.

This work reports a Tunnel field-effect transistor based on Ge-source pocket technique. The main aim is to improve the current ratio and Subthreshold Slope (SS). A dual-material asymmetric dielectric gate has been used to optimize the device performance. The critical parameters such as current ratio, SS, threshold voltage, ambipolarity are studied in this work. This work also includes capacitive analysis of the proposed structure. A comparative analysis with existing structures shows the effectiveness of the proposed work. A significant reduction in SS and threshold voltage is reported in this structure. A current ratio of 1012 is obtained along with much reduction in ambipolarity.

This work demonstrates the influence of electrical noise in a dual dielectric pocket heterojunction silicon-on-insulator (SOI) tunnel field-effect transistor (TFET). Electrical noise behavior is analyzed by considering the low-frequency noise component, flicker noise to remark on reliability aspects of the device. The impact of characteristic deviation is also investigated for various electrical parameters. Further, the device characteristic is explored under the influence of various design parameters.

In recent decades, Micro-total analytical systems (µ-TAS)/lab-on-chip devices with the electrochemical detection scheme have attracted much attention owing to their label-free detection capability and cost-effective instrumentation. In situations like a pandemic, these detection systems become all the more relevant. However, cost-effective microfabrication technique and proper electrode alignment with the microchannel remain a huge challenge. To resolve these issues through a novel approach, we present an efficient and cost-effective method of fabricating various micro-total-analysis systems, employing a fully integrated end-column electrochemical detection (ED) system. In this study, various substrates used while fabricating the microchannel substrates were Glass, Silicon, Polymethyl Methacrylate (PMMA)-sheet, Disposable syringes, micropipette tip, etc. These were finally integrated and aligned at their end-columns with the conductivity electrodes. The microchannels and the spaces for linear-alignment of working-electrode with the channel were fabricated using a simple and single-step process of casting the Polydimethylsiloxane (PDMS) polymer on a micro-scale template like metal wire/nylon thread, and electrode-space-shaping elements, and releasing of all intended micro-structures of devices, in a certain prescribed manner. Due to the simplicity of the single-step fabrication-processes, the microdevices production was quite repeatable without any possible failure resulting in identical dimension fluidic-chips each time, provided that the same sized fabrication-templates were utilized for these procedures. The microelectrode alignment with microchannel endings was efficiently proved by using a simple detection-circuit.

Highly efficient titanium oxide (TiO2) nanowires (NWs) structures were synthesized from pressed and sintered titanium oxide (TiO2) material on a gallium nitride (GaN) wafer inside e-beam evaporation chamber by employing glancing angle deposition (GLAD) technique. The morphological and chemical compositions were studied by the field emission scanning electron microscopy (FE-SEM) and energy dispersive X-ray spectroscopy (EDX). Our results indicated uniform growth and vertical nature of the NWs on GaN wafer. The average diameter of TiO2 NWs is ~32 nm, and the length of the NWs is measured to be ~400 nm. The presence of titanium (Ti), nitrogen (N), gallium (Ga) and oxygen (O) was also evident from the analysis result. The growth mechanisms of TiO2 nanowires (NWs) were also discussed in this work. The band gap of the deposited TiO2 NWs obtained from photoluminescence analysis is ~3.3 eV. The peaks at 396.82 nm (~3.12 eV) and 450.83 nm (~2.75 eV) may be due to the presence of defects in the TiO2. NWs. The deposited TiO2 NWs on GaN substrate may be applicable for optoelectronics application.

Design of a real-time device in the form of a MEMS wearable sensor poses challenge in diverse aspects. To model a device for any required ranges of the parameters, the finite element method helps efficiently as the performance of device, in terms of expected specifications like operating frequency, can be analysed with each changing parameter. Such modelling is described in the present paper throwing light on the performance of a proof mass designed for a capacitive accelerometer. The material used for the proof mass and the supporting beams is same and the frequency of operation of the proof mass in the required eigen mode is less than few tens of Hz. A proof mass designed with four support beams is modelled for low-frequency response. Optimising the geometry of the proof mass has given a frequency response between (2 and 12) Hz and a maximum displacement of 4405 µm. The material used is polycrystalline silicon.

In CZTS-based solar cells, finding an alternative absorber layer material to improve the device performance is ongoing research subject. In this paper, we have identified five alternative absorber layer materials, namely Cu2XSnS4 (X = Fe, Mg, Mn, Ni, Sr) and investigated the devices performance with architecture Al-ZnO/i-ZnO/CdS/Absorber/Mo in SCAPS-1D simulator individually of above said five different absorber materials which has not been reported in literature. All the solar cell devices are then optimized on device level by varying thickness of absorber layer, absorber doping and defect density and absorber/buffer interface defect density. We also observed their impact on solar cell characteristic parameters. A comparative study is also carried out to find applicability of these materials as an alternative absorber layer to CZTS in CZTS-based solar cells.

Wireless implantable medical devices (IMDs) offer immense possibilities in health care. Since IMDs survive on battery energy, they suffer from serious power constraints. While studying the power concerns of IMDs, it is depicted that voltage-controlled oscillator (VCO) is a fundamental component in the transceiver which consumes significant energy compared to other elements. The quality of performance offered by voltage-controlled oscillator (VCO) in turn depends on the characteristics of constituent current mirror circuit section. In this work, an extensive comparison of performance of VCO is carried out for different current mirror designs to ensure the high standards of quality at power supply as low as 1.8 V. All the circuits have been implemented using spice at 0.032 µm TSMC CMOS.

Prompt escalation of technology in the realm of electronics is beyond comparison. Pronounced digital circuits like registers, buffers, counters and sequential state machines make large scale utilization of Delay Flipflop (D flipflop). Subsequently, this work propounds several design facets of a D flipflop. Consequently, a CMOS based conventional NAND circuit is considered and examined for four design parameters namely, delay(tp), power (pwr), Power Delay Product (PDP) and Energy Delay Product (EDP). Moreover, MOS current mode logic (MCML) based implementation is investigated for NAND circuit. In addition to that, this paper also presents a smart logic design of MCML NAND based D flipflop. The broached design results as a competent candidate for countless D flipflop based digital logic designs as it relents exclusive results in contrast to the conventional counterpart. Thus, the proposed enactment broaches as ideal circuit for recent digital logic style applications.

This paper introduces the design and simulation of SPDT-switch having less pull-in voltage and better isolation at 1–25 GHz range. The exhibition of the intended SPDT configuration is such that the signal can be routed within two ports utilizing barely one single-bias. Here, we have designed a non-uniform meander-type shunt switch and these two switches are incorporated on the same single line, which helps to decrease the pull-in voltage, also maintained good isolation and enhance the performance of the switch. The simulation of Electromechanical and Electromagnetic analysis is done in FEM and HFSS tools. However, the switch is obtained a small operating voltage of 2.3 V. The radio frequency characteristics of return (S11) and insertion loss (S12) are measured −32.44 dB, –0.108 dB, and the switch achieves good isolation as −59.94 dB and −42.25 dB at 1–25 GHz. Here, the proposed device is command signals and reduces opposed uniting two shifting components. The overall proposed device is kept better results at 1–25 GHz frequency.

In this paper, design and simulation of three kinds of microcantilevers are done with the use of COMSOL Multiphysics FEM software. The physical behaviour of the 3 microcantilevers and its corresponding response is calculated using three materials zinc oxide, lead zirconate titanate and barium titanate and with three electrodes aluminium, gold and platinum. At most proposed microcantilever is an integrated with electro-osmosis pressure sensor to detect the blood glucose levels in continuous glucose monitoring system in terms of change in resistance and in voltage form.

The aim of this analysis was to investigate the quantum control of Cu2ZnSn(Sx,Se1-x)4, in which the S and Se propositions vary from 0 to 1. The spectral response of solar cells with recombination rate, energy band diagram, quantum efficiency with respect to absorption properties has been studied, resulting in a remarkable efficiency of 42% with a composition value of x = 0.8. The influence was investigated and evaluated mainly by the quantity of wells with a thickness of 10 nm and the different composition values of S/(S + Se). Barrier material CZTS has a wider bandwidth, whereas CZTSxSe1-x material also has a smaller bandwidth than the surrounding material to absorb photons at both lower frequency and higher frequency. With 45.702 (mA/cm2) Jsc and 1.03 V Voc, this analytic approach achieves optimum efficiency at 38%.

In this paper, flip flop-based frequency divider is proposed which is suitable for low voltage and low power design. Frequency divider is implemented using CNTFET-based master slave D-FF. For the design of frequency divider, various design parameters as delay in propagation (tp), power dissipation (pwr), Power Delay Product (PDP) and Energy Delay Product (EDP) are studied for a conventional master slave D-FF. These metrics are compared with design metrics of CNTFET (Carbon Nano-Tube Field Effect Transistor)-based master slave D-FF. Simulation results show that the CNTFET-based master slave D-FF offers high speed and less power dissipation. This research work proposes a power efficient frequency divider design that has total power consumption as low as 0.144 µW for 0.7 V supply. All the simulations are performed on HSPICE simulator at 22 nm technology.

Multiplier plays a vital role in different applications hence more number of multiplier applications are available, as there is a high requirement of multipliers in the various applications, it is required to develop a high speed and area efficient multiplier. This article explains the design and development of high speed and area efficient multiplier using Verilog. In this work, a new 16 bit multiplication unit has been designed and implemented. The proposed multiplier will incorporate for developing the multiplier and it will be using a binary coded decimal adder and carry skip adder, and CSKA has a higher speed and lower energy consumption. For calculating multiples of multiplicand BCD Adder will be used and for calculating sum of partial products CSKA Adder will be used. Parallel path is used for carry propagation in the carry skip adder. Hence, time taken for propagation delay can be reduced in the adder. 16-bit Multipliers is designed, implemented and explained in this paper. The important factors need to improve for designing multiplier is less area, high speed and low power.

This paper presents a novel simulation model of an X-shaped linear piezoelectric energy harvester for wideband applications. Moreover, the physical dimensions and material properties are taken as same as used in nonlinear H-shaped multimodal, which is experimentally analyzed in the literature. The designed FEM harvester model is analyzed for wideband applications in terms of displacement, optimum load resistance, maximum electrical and mechanical output powers, and efficiency. Furthermore, the results show that the novel X-shaped linear piezoelectric energy harvester produces more electrical response and efficiency. Finally, this work can be extended for the development of a numerical model with practical implementation in wideband applications.

Reversible logic is becoming one of the highlights of innovative research trends in recent times. It has proved to be a promising candidate for the applications in nanotechnology, quantum computations, and low-power CMOS devices. The need for miniaturization and low power electronics is an ever-emerging research area in lowering power consumption and heat dissipation. In this paper, we are introducing an efficient design approach for a reversible full-adder. This is achieved by introducing a new universal gate called Tuned Fredkin Gate (TFG), which is able to synthesize any Boolean function. Quantum realization of Feynman, Fredkin, and also TFG gate is presented here. The proposed full-adder design outperforms various existing designs based on quantum measures like quantum cost (QC), ancilla inputs (Constant inputs), garbage outputs (GO), and delay. It has shown a reduction in quantum cost by 1 unit, in constant input by 100%, in garbage output by 50%, and in delay by two gate counts. The performance analysis was carried out in Xilinx Vivado 2016.1 environment using Verilog. Moreover, the simplicity in the design structure compared with the existing counterparts makes it a viable choice over other existing ones.

With the advancement of technology, there is a need for high-speed multipliers in every processor. Since multiplication is nothing but a series of addition and shifting operations, the multiplier's speed also depends on its adder. Vedic multiplication is an interesting research topic that gives faster multiplication results, and carry save adder is one of the advanced and fastest adders. In this paper, we are integrating the Vedic multiplication technique, namely Urdhya Thiryagbhyam and carry save adder, to get faster results. Using the proposed 32-bit Vedic multiplier (VM), delay and area are reduced by 39 and 44% in that order compared to the existing 32-bit Vedic multiplier (VM).

This paper presents design and simulation of RF-MEMS capacitive type shunt switch. The main parameters of electromagnetic and electromechanical analysis are performed by utilizing COMSOL and HFSS tools. The performance of the switch is enhanced by including perforation and non-uniform meandering technique. Here, to design an RF-MEMS switch with a change in dimensions and different air gaps, and thickness of the beam for low frequency applications. The actuation voltage of the proposed switch having 10.6 V, the upstate capacitance is 6 × 10^−15. The stress of the beam was obtained as 41.7 MPa. The switch has shown higher isolation and lower insertion loss while implementing the microwave and mm-wave circuits. The S-parameters like return and insertion losses are having −22.37 dB, −0.11 dB, the isolation is obtained −21.89 dB at 2 GHz frequency.

A evolution in VLSI technology takes place, aspect of electronic devices scales down gradually. Scaling in electronic device offers improvement in speed, cell density and storage capacity in DRAM arrays. Leakages in MOS transistor surge as the MOS transistor scales down. The performance analysis of 1T1C DRAM cell is affected due to various leakage sources in MOS transistor. The intention of this paper is to present variation in capacitor value effects on behavior of leakage current, leakage power, retention time and refresh frequency (Frefresh) in 1T1C DRAM cell. This paper investigates the performance of DRAM cell in terms of leakage parameters, retention time (Th) and refresh frequency (Frefresh) with variation of capacitor values (Cs). While capacitor value increases, leakage parameter minimizes; correspondingly, retention time improvement is possible. Design and simulation of DRAM cell for variable values of capacitor were performed with the assistance of cadence tool at 180 nm technology.

This paper proposes a framework of intelligent approach for autonomous parking of the robot. It addresses the challenges of service robots parking in real-time indoor environment. A versatile automatic parking system is developed based on two key approaches, which can able to perform in real-time conditions, 1. Self-exploration of indoor environment for recognition of parking space by autonomous robot and 2. Road map for parking of autonomous robot using intelligent methods. Hardware schemes have been developed for self-exploration by a robot, and it is executed based on the tree-based algorithm and road map for parking of robot is performed by intelligent traversing methods. The FPGA-based robot is used for the validation of self-autonomous parking methods. Xilinx tools have been used for simulation, synthesis and implemented autonomous parking using ZedBoard Zynq-7000 FPGA.

This article presents a real-time early flood monitoring cum warning system in flood-prone areas. The proposed system comprises of three chief constituents, namely sensor network, computing/transmission unit, and database/application server. The real-time information of water conditions is supervised remotely via a wireless sensor network. The data obtained from the hardware system are stored in the cloud and compared with the real-time data of rainfall, emergency flood level, etc. from state meteorological center. The network system decides whether there is an emergency and sends warnings in the form of text messages to the people nearby flood-prone areas.

Vibration energy harvesting (VEH) is viable solution for battery free and self-powered micro-/nano-systems. The ambient vibration available for harvesting is low, random and broad. Hybrid energy harvester provides an alternative to narrow bandwidth, high operational frequency and low-power density VEH. In this paper, nonlinear hybrid vibration energy is developed by integrating both piezoelectric and electromagnetic VEH. The piezoelectric energy harvester and electromagnetic harvester is optimized for low frequency and maximum power generation configuration. The device is designed for maximum stretching-induced nonlinearity and repulsive magnetic nonlinearity to achieve bistable-quartic (BQT) potential. The potential profile and restoring force is studied to show enhanced performance of the device. When excited at the natural frequency of 59 Hz and acceleration amplitude of 0.5 g, a total voltage generation of 2.6 V (Piezoelectric voltage = 1.8 V and induced electromagnetic voltage = 0.8 V) is reported. The hybrid design enhances the frequency bandwidth, power generation and off-resonance operation making it efficient to be used in broadband random vibration environments.

A 1 KB static random access memory (SRAM) and its control circuit are designed to be implemented in 180 nm technology. Designed SRAM is working on 200 MHz and exhibited good memory cell stability. Overall SRAM architecture was implemented using 6 transistors (6 T) memory cells accessed by row and column decoders. Control logic architecture was also implemented to perform read and write operations using sense amplifier and write driver circuits, respectively. The circuit achieved memory access time of 2.7 ns, which is among the lower values from many earlier published reports for similar technologies, while consuming 5.2 mW power for one byte.

In this work, α-form and β-form of copper (II) phthalocyanine (CuPc) were used for fabrication of OFET devices and the corresponding electrical performance was studied. OFETs with α-form CuPc were found to exhibit better device performance with an average mobility of 4.7(±1.0) × 10–3 cm2V−1 s−1 compared with β-form with an average mobility of 0.9(±0.2) × 10–3 cm2 V−1 s−1. The better device performance of α-form CuPc OFETs was attributed jointly due to thinner active semiconductor and better film uniformity in α-form CuPc OFETs over β-form devices.