Multi-core Processor Scheduling with Respect to Data Bus Bandwidth

The chapter delves into the complexities of scheduling software modules on multi-core processors, with a specific focus on the constraints imposed by the data bus bandwidth. It introduces two problem formulations, demonstrating the NP-hardness of the scheduling problem and proposing a mixed integer linear programming model for one formulation. Additionally, a greedy algorithm is presented for the second formulation, offering a practical approach to approximate solutions. The chapter also includes computational experiments and real-life data generation methods, highlighting the effectiveness and accuracy of the proposed algorithms. The results show that the greedy algorithm provides high-quality solutions with a low computational cost, making it a valuable tool for practitioners in the field.